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| M PIC18FXX8 Data Sheet High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN 2002 Microchip Technology Inc. Preliminary DS41159B Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. * * * If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. DS41159B - page ii Preliminary 2002 Microchip Technology Inc. M PIC18FXX8 Advanced Analog Features: * 10-bit, up to 8-channel Analog-to-Digital Converter module (A/D) with: - Conversion available during SLEEP - Up to 8 channels available * Analog Comparator Module: - Programmable input and output multiplexing * Comparator Voltage Reference Module * Programmable Low Voltage Detection (LVD) module - Supports interrupt on low voltage detection * Programmable Brown-out Reset (BOR) High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN High Performance RISC CPU: * Linear program memory addressing up to 2 Mbytes * Linear data memory addressing to 4 Kbytes * Up to 10 MIPs operation * DC - 40 MHz clock input * 4 MHz - 10 MHz osc./clock input with PLL active * 16-bit wide instructions, 8-bit wide data path * Priority levels for interrupts * 8 x 8 Single Cycle Hardware Multiplier Peripheral Features: * High current sink/source 25 mA/25 mA * Three external interrupt pins * Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler * Timer1 module: 16-bit timer/counter * Timer2 module: 8-bit timer/counter with 8-bit period register (time-base for PWM) * Timer3 module: 16-bit timer/counter * Secondary oscillator clock option - Timer1/Timer3 * Capture/Compare/PWM (CCP) modules CCP pins can be configured as: - Capture input: 16-bit, max resolution 6.25 ns - Compare: 16-bit, max resolution 100 ns (TCY) - PWM output: PWM resolution is 1- to 10-bit Max. PWM freq. @:8-bit resolution = 156 kHz 10-bit resolution = 39 kHz * Enhanced CCP module which has all the features of the standard CCP module, but also has the following features for advanced motor control: - 1, 2, or 4 PWM outputs - Selectable PWM polarity - Programmable PWM deadtime * Master Synchronous Serial Port (MSSP) with two modes of operation: - 3-wire SPITM (Supports all 4 SPI modes) - I2CTM Master and Slave mode * Addressable USART module: Supports Interrupt on Address bit CAN bus Module Features: * Message bit rates up to 1 Mbps * Conforms to CAN 2.0B ACTIVE Spec with: - 29-bit Identifier Fields - 8-byte message length - 3 Transmit Message Buffers with prioritization - 2 Receive Message Buffers - 6 full 29-bit Acceptance Filters - Prioritization of Acceptance Filters - Multiple Receive Buffers for High Priority Messages to prevent loss due to overflow - Advanced Error Management Features Special Microcontroller Features: * Power-on Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options, including: - 4X Phase Lock Loop (of primary oscillator) - Secondary Oscillator (32 kHz) clock input * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins FLASH Technology: * * * * Low power, high speed Enhanced FLASH technology Fully static design Wide operating voltage range (2.0V to 5.5V) Industrial and Extended temperature ranges 2002 Microchip Technology Inc. Preliminary DS41159B-page 1 PIC18FXX8 Comparators Program Memory Device FLASH (bytes) 16K 32K 16K 32K Data Memory I/O 10-bit A/D (ch) 5 5 8 8 MSSP CCP/ ECCP (PWM) 1/0 1/0 1/1 1/1 SPI Y Y Y Y Master I2C Y Y Y Y USART Timers 8/16-bit # Single SRAM EEPROM Word (bytes) (bytes) Instructions 8192 16384 8192 16384 768 1536 768 1536 256 256 256 256 PIC18F248 PIC18F258 PIC18F448 PIC18F458 22 22 33 33 -- -- 2 2 Y Y Y Y 1/3 1/3 1/3 1/3 Pin Diagrams PDIP MCLR/VPP RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RE0/AN5/RD RE1/AN6/WR/C1OUT RE2/AN7/CS/C2OUT VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RD0/PSP0/C1IN+ RD1/PSP1/C1IN1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5/PGM RB4 RB3/CANRX RB2/CANTX/INT2 RB1/INT1 RB0/INT0 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ PIC18F458 PIC18F448 RA4/T0CKI RA5/AN4/SS/LVDIN RE0/AN5/RD RE1/AN6/WR/C1OUT RE2/AN7/CS/C2OUT VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CK1 NC 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0/CVREF MCLR/VPP NC RB7/PGD RB6/PGC RB5/PGM RB4 NC PLCC PIC18F448 PIC18F458 RB3/CANRX RB2/CANTX/INT2 RB1/INT1 RB0/INT0 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RD0/PSP0/C1IN+ RD1/PSP1/C1INRD2/PSP2/C2IN+ RD3/PSP3/C2INRC4/SDI/SDA RC5/SDO RC6/TX/CK NC 18 19 20 21 22 23 24 25 26 27 28 DS41159B-page 2 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 Pin Diagrams (Continued) TQFP RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI NC RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PIC18F448 PIC18F458 SPDIP, SOIC MCLR/VPP RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ NC NC RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP 12 13 14 15 16 17 18 19 20 21 22 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI VSS VDD RE2/AN7/CS/C2OUT RE1/AN6/WR/C1OUT RE0//AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5/PGM RB4 RB3/CANRX RB2/CANTX/INT2 RB1/INT1 RB0/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 2002 Microchip Technology Inc. Preliminary PIC18F258 PIC18F258 DS41159B-page 3 PIC18FXX8 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 17 3.0 Reset .......................................................................................................................................................................................... 25 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Data EEPROM Memory ............................................................................................................................................................ 59 6.0 FLASH Program Memory ........................................................................................................................................................... 65 7.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 75 8.0 Interrupts .................................................................................................................................................................................... 77 9.0 I/O Ports ..................................................................................................................................................................................... 93 10.0 Parallel Slave Port .................................................................................................................................................................... 105 11.0 Timer0 Module ......................................................................................................................................................................... 107 12.0 Timer1 Module ......................................................................................................................................................................... 111 13.0 Timer2 Module ......................................................................................................................................................................... 115 14.0 Timer3 Module ......................................................................................................................................................................... 117 15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 121 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 129 17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 141 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 181 19.0 CAN Module ............................................................................................................................................................................. 197 20.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................................................................................... 237 21.0 Comparator Module.................................................................................................................................................................. 245 22.0 Comparator Voltage Reference Module ................................................................................................................................... 251 23.0 Low Voltage Detect .................................................................................................................................................................. 255 24.0 Special Features of the CPU .................................................................................................................................................... 261 25.0 Instruction Set Summary .......................................................................................................................................................... 277 26.0 Development Support............................................................................................................................................................... 319 27.0 Electrical Characteristics .......................................................................................................................................................... 325 28.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 355 29.0 Packaging Information.............................................................................................................................................................. 357 Appendix A: Data Sheet Revision History.......................................................................................................................................... 365 Appendix B: Device Differences......................................................................................................................................................... 365 Appendix C: Device Migrations .......................................................................................................................................................... 366 Appendix D: Migrating from other PICmicro Devices......................................................................................................................... 366 Appendix E: Development Tool Version Requirements ..................................................................................................................... 367 Index .................................................................................................................................................................................................. 369 On-Line Support................................................................................................................................................................................. 379 Reader Response .............................................................................................................................................................................. 380 PIC18FXX8 Product Identification System......................................................................................................................................... 381 DS41159B-page 4 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2002 Microchip Technology Inc. Preliminary DS41159B-page 5 PIC18FXX8 NOTES: DS41159B-page 6 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 1.0 DEVICE OVERVIEW 2. 3. 4. This document contains device specific information for the following devices: 1. 2. 3. 4. PIC18F248 PIC18F258 PIC18F448 PIC18F458 PIC18F2X8 devices implement 5 A/D channels, as opposed to 8 for PIC18F4X8 devices. PIC18F2X8 devices implement 3 I/O ports, while PIC18F4X8 devices implement 5. Only PIC18F4X8 devices implement the Enhanced CCP module, analog comparators and the Parallel Slave Port. These devices are available in 28-pin, 40-pin and 44-pin packages. They are differentiated from each other in four ways: 1. PIC18FX58 devices have twice the FLASH program memory and data RAM of PIC18FX48 devices (32 Kbytes and 1536 bytes vs. 16 Kbytes and 768 bytes, respectively). All other features for devices in the PIC18FXX8 family, including the serial communications modules, are identical. These are summarized in Table 1-1. Block diagrams of the PIC18F2X8 and PIC18F4X8 devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2. TABLE 1-1: PIC18FXX8 DEVICE FEATURES Features PIC18F248 DC - 40 MHz 16K 8192 768 256 17 Ports A, B, C 4 1 -- PIC18F258 DC - 40 MHz 32K 16384 1536 256 17 Ports A, B, C 4 1 -- PIC18F448 DC - 40 MHz 16K 8192 PIC18F458 DC - 40 MHz 32K 16384 Operating Frequency Internal Program Bytes Memory # of Single Word Instructions Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications 768 1536 256 256 21 21 Ports A, B, C, D, E Ports A, B, C, D, E 4 4 1 1 1 1 MSSP, CAN, Addressable USART Yes 8 input channels 2 Yes POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST) Yes Yes Yes Yes 75 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP Parallel Communications (PSP) 10-bit Analog-to-Digital Converter Analog Comparators Analog Comparators VREF Output RESETS (and Delays) Programmable Low Voltage Detect Programmable Brown-out Reset CAN Module In-Circuit Serial ProgrammingTM (ICSPTM) Instruction Set Packages MSSP, CAN, MSSP, CAN, MSSP, CAN, Addressable Addressable Addressable USART USART USART No No Yes 5 input channels 5 input channels 8 input channels No No 2 N/A N/A Yes POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) (PWRT, OST) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 75 Instructions 28-pin SPDIP 28-pin SOIC 75 Instructions 28-pin SPDIP 28-pin SOIC 75 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP 2002 Microchip Technology Inc. Preliminary DS41159B-page 7 PIC18FXX8 FIGURE 1-1: PIC18F248/258 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 21 21 inc/dec logic 8 Data Latch Data RAM up to 1536 bytes Address Latch PCLATU PCLATH PCU PCH PCL Program Counter Address Latch Program Memory up to 32 Kbytes Data Latch Decode Table Latch 16 8 ROM Latch inc/dec logic PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 PRODH PRODL Instruction Decode & Control OSC2/CLKO/RA6 OSC1/CLKI Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Test Mode Select 8 x 8 Multiply 3 BITOP 8 8 ALU<8> 8 W 8 8 8 31 Level Stack 12 Address<12> 4 BSR 12 4 FSR0 Bank0, F FSR1 FSR2 12 PORTB RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX RB4 RB5/PGM RB6/PGC RB7/PGD RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN OSC2/CLKO/RA6 IR T1OSI T1OSO 4X PLL Precision Bandgap Reference Bandgap MCLR VDD, VSS PBOR PLVD Timer0 Timer1 Timer2 Timer3 10-bit ADC Data EEPROM CCP1 USART Synchronous Serial Port CAN Module DS41159B-page 8 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 1-2: PIC18F448/458 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 21 21 inc/dec logic 8 Data Latch Data RAM up to 1536 Kbytes Address Latch PCLATU PCLATH PCU PCH PCL Program Counter Address Latch Program Memory up to 32 Kbytes Data Latch Table Latch 16 8 ROM Latch Decode 31 Level Stack 12 Address<12> 4 BSR 12 4 FSR0 Bank0, F FSR1 FSR2 12 PORTB RB0/INT0 RB1/INT1 RB2/CANTX/INT2 RB3/CANRX RB4 RB5/PGM RB6/PGC RB7/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 PRODH PRODL Instruction Decode & Control OSC2/CLKO/RA6 OSC1/CLKI Timing Generation T1OSI T1OSO 4X PLL Precision Bandgap Reference Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Test Mode Select 8 x 8 Multiply 3 BITOP 8 8 ALU<8> 8 W 8 8 8 PORTD RD0/PSP0/C1IN+ RD1/PSP1/C1INRD2/PSP2/C2IN+ RD3/PSP3/C2INRD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D PORTE RE0/AN5/RD RE1/AN6/WR//C1OUT RE2/AN7/CS/C2OUT RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN OSC2/CLKO/RA6 inc/dec logic IR Bandgap MCLR VDD, VSS USART Timer2 PBOR PLVD Timer0 Timer1 Timer3 10-bit ADC Parallel Slave Port Data EEPROM Comparators CCP1 Enhanced CCP USART Synchronous Serial Port CAN Module 2002 Microchip Technology Inc. Preliminary DS41159B-page 9 PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F248/258 SPDIP, SOIC MCLR/VPP MCLR 1 PIC18F448/458 PDIP 1 TQFP 18 PLCC 2 I ST Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. These pins should be left unconnected. Pin Type Buffer Type Description VPP NC OSC1/CLKI OSC1 -- 9 -- 13 12, 13, 1, 17, 33, 34 28, 40 30 14 P -- -- -- I CLKI I Oscillator crystal or external clock input. Oscillator crystal input or CMOS/ST external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. CMOS External clock source input. Always associated with pin function OSC1 (see OSC1/ CLKI, OSC2/CLKO pins). -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. OSC2/CLKO/RA6 OSC2 10 14 31 15 O CLKO O -- RA6 Legend: TTL = ST = I = P= TTL compatible input Schmitt Trigger input with CMOS levels Input Power I/O CMOS Analog O OD = = = = TTL CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) DS41159B-page 10 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC RA0/AN0/CVREF RA0 AN0 CVREF RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5/AN4/SS/LVDIN RA5 AN4 SS LVDIN RA6 Legend: TTL = ST = I = P= TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD = = = = 7 7 24 8 I/O I I I TTL Analog ST Analog Digital I/O. Analog input 4. SPI slave select input. Low voltage detect input. See the OSC2/CLKO/RA6 pin. CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) 2 PIC18F448/458 PDIP 2 TQFP 19 PLCC PORTA is a bi-directional I/O port. 3 I/O I O 3 3 20 4 I/O I 4 4 21 5 I/O I I 5 5 22 6 I/O I I 6 6 23 7 I/O I TTL/OD ST Digital I/O - open drain when configured as output. Timer0 external clock input. TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (High) input. TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (Low) input. TTL Analog Digital I/O. Analog input 1. TTL Analog Analog Digital I/O. Analog input 0. Comparator voltage reference output. Pin Type Buffer Type Description 2002 Microchip Technology Inc. Preliminary DS41159B-page 11 PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC PIC18F448/458 PDIP TQFP PLCC PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/CANTX/INT2 RB2 CANTX INT2 RB3/CANRX RB3 CANRX RB4 RB5/PGM RB5 PGM RB6/PGC RB6 27 39 16 43 I/O TTL Digital I/O. In-Circuit Debugger pin. Interrupt-on-change pin. ICSP programming clock. 21 33 8 36 I/O I 22 34 9 37 I/O I 23 35 10 38 I/O O I 24 36 11 39 I/O I 25 26 37 38 14 15 41 42 I/O I TTL ST Digital I/O. Interrupt-on-change pin. Low voltage ICSP programming enable. I/O TTL TTL TTL Digital I/O. Receive signal for CAN bus. Digital I/O. Interrupt-on-change pin. TTL TTL ST Digital I/O. Transmit signal for CAN bus. External interrupt 2. TTL ST Digital I/O. External interrupt 1. TTL ST Digital I/O. External interrupt 0. Pin Type Buffer Type Description PGC RB7/PGD RB7 28 40 17 44 I ST I/O TTL PGD Legend: TTL = ST = I = P= TTL compatible input Schmitt Trigger input with CMOS levels Input Power I/O CMOS Analog O OD = = = = ST Digital I/O. In-Circuit Debugger pin. Interrupt-on-change pin. ICSP programming data. CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) DS41159B-page 12 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI RC1 T1OSI RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: TTL = ST = I = P= 18 26 1 29 I/O I I/O TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD = = = = ST ST ST Digital I/O. USART asynchronous receive. USART synchronous data (see TX/CK). 15 23 42 25 I/O I I/O 16 24 43 26 I/O O 17 25 44 27 I/O O I/O ST -- ST Digital I/O. USART asynchronous transmit. USART synchronous clock (see RX/DT). ST -- Digital I/O. SPI data out. ST ST ST Digital I/O. SPI data in. I2C data I/O. 11 PIC18F448/458 PDIP 15 TQFP 32 PLCC PORTC is a bi-directional I/O port. 16 I/O O I 12 16 35 18 I/O I 13 17 36 19 I/O I/O 14 18 37 20 I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST CMOS Digital I/O. Timer1 oscillator input. ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Pin Type Buffer Type Description CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) 2002 Microchip Technology Inc. Preliminary DS41159B-page 13 PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC PIC18F448/458 PDIP TQFP PLCC PORTD is a bi-directional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/PSP0/C1IN+ RD0 PSP0 C1IN+ RD1/PSP1/C1INRD1 PSP1 C1INRD2/PSP2/C2IN+ RD2 PSP2 C2IN+ RD3/PSP3/C2INRD3 PSP3 C2INRD4/PSP4/ECCP1/ P1A RD4 PSP4 ECCP1 P1A RD5/PSP5/P1B RD5 PSP5 P1B RD6/PSP6/P1C RD6 PSP6 P1C RD7/PSP7/P1D RD7 PSP7 P1D Legend: TTL = ST = I = P= -- 19 38 21 I/O I/O I -- 20 39 22 I/O I/O I -- 21 40 23 I/O I/O I -- 22 41 24 I/O I/O I -- 27 2 30 I/O I/O I/O O -- 28 3 31 I/O I/O O -- 29 4 32 I/O I/O O -- 30 5 33 I/O I/O O TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD = = = = ST TTL -- Digital I/O. Parallel slave port data. ECCP1 PWM output D. ST TTL -- Digital I/O. Parallel slave port data. ECCP1 PWM output C. ST TTL -- Digital I/O. Parallel slave port data. ECCP1 PWM output B. ST TTL ST -- Digital I/O. Parallel slave port data. ECCP1 capture/compare. ECCP1 PWM output A. ST TTL Analog Digital I/O. Parallel slave port data. Comparator 2 input. ST TTL Analog Digital I/O. Parallel slave port data. Comparator 2 input. ST TTL Analog Digital I/O. Parallel slave port data. Comparator 1 input. ST TTL Analog Digital I/O. Parallel slave port data. Comparator 1 input. Pin Type Buffer Type Description CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) DS41159B-page 14 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F248/258 SPDIP, SOIC RE0/AN5/RD RE0 AN5 RD RE1/AN6/WR/C1OUT RE1 AN6 WR C1OUT RE2/AN7/CS/C2OUT RE2 AN7 CS -- 10 27 11 I/O I I ST Analog TTL Digital I/O. Analog input 7. Chip select control for parallel slave port (see RD and WR pins). Comparator 2 output. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. -- PIC18F448/458 PDIP 8 TQFP 25 PLCC PORTE is a bi-directional I/O port. 9 I/O I I -- 9 26 10 I/O I I O ST Analog TTL Analog Digital I/O. Analog input 6. Write control for parallel slave port (see CS and RD pins). Comparator 1 output. ST Analog TTL Digital I/O. Analog input 5. Read control for parallel slave port (see WR and CS pins). Pin Type Buffer Type Description C2OUT VSS VDD Legend: TTL = ST = I = P= 19, 8 20 12, 31 11, 32 6, 29 7, 28 13, 34 12, 35 O -- -- = = = = Analog -- -- TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) 2002 Microchip Technology Inc. Preliminary DS41159B-page 15 PIC18FXX8 NOTES: DS41159B-page 16 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 2.0 2.1 OSCILLATOR CONFIGURATIONS Oscillator Types FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 To Internal Logic SLEEP The PIC18FXX8 can be operated in one of eight Oscillator modes, programmable by three configuration bits (FOSC2, FOSC1, and FOSC0). 1. 2. 3. 4. 5. 6. 7. 8. LP XT HS HS4 RC RCIO EC ECIO Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator High Speed Crystal/Resonator with PLL enabled External Resistor/Capacitor External Resistor/Capacitor with I/O pin enabled External Clock External Clock with I/O pin enabled C1(1) XTAL RS(2) C2(1) OSC2 RF(3) PIC18FXX8 Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen. 2.2 Crystal Oscillator/Ceramic Resonators TABLE 2-1: CERAMIC RESONATORS Ranges Tested: In XT, LP, HS or HS4 (PLL) Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. An external clock source may also be connected to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4. The PIC18FXX8 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. Mode XT Freq OSC1 OSC2 455 kHz 68 - 100 pF 68 - 100 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 4.0 MHz 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 68 pF HS 8.0 MHz 16.0 MHz 10 - 22 pF 10 - 22 pF TBD TBD 20.0 MHz 25.0 MHz TBD TBD HS+PLL 4.0 MHz TBD TBD 8.0 MHz 10 - 68 pF 10 - 68 pF 10.0 MHz TBD TBD These values are for design guidance only. See notes following Table 2-2. Resonators Used: 455 kHz Panasonic EFO-A455K04B 0.3% 2.0 MHz Murata Erie CSA2.00MG 0.5% 4.0 MHz Murata Erie CSA4.00MG 0.5% 8.0 MHz Murata Erie CSA8.00MT 0.5% 16.0 MHz Murata Erie CSA16.00MX 0.5% All resonators used did not have built-in capacitors. 2002 Microchip Technology Inc. Preliminary DS41159B-page 17 PIC18FXX8 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq 32.0 kHz 200 kHz XT 200 kHz 1.0 MHz 4.0 MHz HS 4.0 MHz 8.0 MHz 20.0 MHz 25.0 MHz HS+PLL 4.0 MHz 8.0 MHz 10.0 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF TBD 15 pF 15-33 pF TBD Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF TBD 15 pF 15-33 pF TBD 2.3 RC Oscillator Osc Type LP For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 2-2 shows how the RC combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. These values are for design guidance only. See notes on this page. Crystals Used 32.0 kHz 200 kHz 1.0 MHz 4.0 MHz 8.0 MHz 20.0 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000MC 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM FIGURE 2-2: VDD REXT RC OSCILLATOR MODE PIC18FXX8 OSC1 Internal Clock CEXT VSS FOSC/4 Recommended values: OSC2/CLKO 3 k REXT 100 k CEXT > 20 pF Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 2-1). 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. The RCIO Oscillator mode functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. DS41159B-page 18 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 2.4 External Clock Input FIGURE 2-4: The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode. EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1 Clock from Ext. System PIC18FXX8 I/O (OSC2) 2.5 HS4 (PLL) FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC OSC CONFIGURATION) OSC1 Clock from Ext. System FOSC/4 PIC18FXX8 A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due to high frequency crystals. The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1. The PLL is one of the modes of the FOSC2:FOSC0 configuration bits. The Oscillator mode is specified during device programming. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out referred to as TPLL. OSC2 The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. Figure 2-4 shows the pin connections for the ECIO Oscillator mode. FIGURE 2-5: PLL BLOCK DIAGRAM FOSC2:FOSC0 = `110' OSC2 Phase Comparator FIN Crystal Osc FOUT Loop Filter VCO MUX SYSCLK OSC1 Divide by 4 2002 Microchip Technology Inc. Preliminary DS41159B-page 19 PIC18FXX8 2.6 Oscillator Switching Feature 2.6.1 SYSTEM CLOCK SWITCH BIT The PIC18FXX8 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18FXX8 devices, this alternate clock source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a Low Power Execution mode. Figure 2-6 shows a block diagram of the system clock sources. The clock switching feature is enabled by programming the Oscillator Switching Enable (OSCSEN) bit in Configuration register, CONFIG1H, to a '0'. Clock switching is disabled in an erased device. See Section 12.2 for further details of the Timer1 oscillator, and Section 24.1 for Configuration Register details. The system clock source switching is performed under software control. The system clock switch bit, SCS (OSCCON register), controls the clock switching. When the SCS bit is '0', the system clock source comes from the main oscillator selected by the FOSC2:FOSC0 configuration bits. When the SCS bit is set, the system clock source comes from the Timer1 oscillator. The SCS bit is cleared on all forms of RESET. Note: The Timer1 oscillator must be enabled to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 control register (T1CON). If the Timer1 oscillator is not enabled, any write to the SCS bit will be ignored (SCS bit forced cleared) and the main oscillator continues to be the system clock source. FIGURE 2-6: DEVICE CLOCK SOURCES PIC18FXX8 Main Oscillator OSC2 SLEEP OSC1 Timer 1 Oscillator T1OSO T1OSCEN Enable Oscillator Clock Source Option for Other Modules Note: I/O pins have diode protection to VDD and VSS. 4 x PLL TOSC TT1P TOSC/4 TSCLK T1OSI Clock Source MUX REGISTER 2-1: OSCCON REGISTER U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SCS bit 0 bit 7-1 bit 0 Unimplemented: Read as '0' SCS: System Clock Switch bit When OSCSEN configuration bit = '0' and T1OSCEN bit is set: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When OSCSEN is clear or T1OSCEN is clear: Bit is forced clear Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 20 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 2.6.2 OSCILLATOR TRANSITIONS The PIC18FXX8 devices contain circuitry to prevent "glitches" when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Figure 2-7 shows a timing diagram indicating the transition from the main oscillator to the Timer1 oscillator. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place. If the main oscillator is configured for an external crystal (HS, XT, LP), the transition will take place after an oscillator start-up time (TOST) has occurred. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT, and LP modes is shown in Figure 2-8. FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 TT1P 1 2 3 4 Tscs Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 TOSC Internal System Clock SCS (OSCCON<0>) Program Counter PC 5 6 7 8 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 TDLY PC + 2 PC + 4 Note 1: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-8: Q3 T1OSI OSC1 TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 1 TOST 2 3 4 5 TSCS 6 7 8 OSC2 Internal System Clock SCS (OSCCON<0>) Program Counter TOSC PC PC + 2 PC + 4 Note 1: TOST = 1024 TOSC (drawing not to scale). 2002 Microchip Technology Inc. Preliminary DS41159B-page 21 PIC18FXX8 If the main oscillator is configured for HS4 (PLL) mode, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-9. If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes is shown in Figure 2-10. FIGURE 2-9: Q4 T1OSI OSC1 TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST OSC2 PLL Clock Input Internal System Clock SCS (OSCCON<0>) Program Counter PC TPLL TOSC 1 2 3 TSCS 4 5 6 7 8 PC + 2 PC + 4 Note 1: TOST = 1024 TOSC (drawing not to scale). FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P TOSC 1 2 3 4 5 6 7 8 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 OSC2 Internal System Clock SCS (OSCCON<0>) TSCS Program Counter PC PC + 2 PC + 4 Note 1: RC Oscillator mode assumed. DS41159B-page 22 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 2.7 Effects of SLEEP Mode on the On-Chip Oscillator RESET until the device power supply and clock are stable. For additional information on RESET operation, see Section 3.0. The first timer is the Power-up Timer (PWRT), which optionally provides a fixed delay of TPWRT (parameter #D033) on power-up only (POR and BOR). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. With the PLL enabled (HS4 Oscillator mode), the timeout sequence following a Power-on Reset is different from other Oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time delay has expired, then the Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional time-out. This time is called TPLL (parameter #7) to allow the PLL ample time to lock to the incoming clock frequency. When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during SLEEP will increase the current consumed during SLEEP. The user can wake from SLEEP through external RESET, Watchdog Timer Reset, or through an interrupt. 2.8 Power-up Delays Power-up delays are controlled by two timers, so that no external RESET circuitry is required for most applications. The delays ensure that the device is kept in TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC1 Pin Floating, external resistor should pull high Floating, external resistor should pull high Floating Floating Feedback inverter disabled, at quiescent voltage level At logic low Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low Feedback inverter disabled, at quiescent voltage level OSC2 Pin OSC Mode RC RCIO ECIO EC LP, XT, and HS Note: See Table 3-1 in Section 3.0, for time-outs due to SLEEP and MCLR Reset. 2002 Microchip Technology Inc. Preliminary DS41159B-page 23 PIC18FXX8 NOTES: DS41159B-page 24 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 3.0 RESET The PIC18FXX8 differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset during normal operation Programmable Brown-out Reset (PBOR) RESET Instruction Stack Full Reset Stack Underflow Reset state on Power-on Reset, MCLR, WDT Reset, Brownout Reset, MCLR Reset during SLEEP and by the RESET instruction. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR are set or cleared differently in different RESET situations, as indicated in Table 3-2. These bits are used in software to determine the nature of the RESET. See Table 3-3 for a full description of the RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 3-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. A WDT Reset does not drive MCLR pin low. Most registers are unaffected by a RESET. Their status is unknown on POR and unchanged by all other RESETS. The other registers are forced to a "RESET" FIGURE 3-1: RESET Instruction SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Stack Pointer Stack Full/Underflow Reset External Reset MCLR WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT OST SLEEP WDT Time-out Reset Power-on Reset BOREN S 10-bit Ripple Counter OSC1 PWRT On-chip RC OSC(1) 10-bit Ripple Counter Chip_Reset R Q Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2002 Microchip Technology Inc. Preliminary DS41159B-page 25 PIC18FXX8 3.1 Power-on Reset (POR) 3.3 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when a VDD rise is detected. To take advantage of the POR circuitry, connect the MCLR pin directly (or through a resistor) to VDD. This eliminates external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (refer to parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the voltage start-up condition. The Power-up Timer provides a fixed nominal time-out (parameter #33), only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit (PWRTEN in CONFIG2L register) is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See DC parameter #33 for details. 3.4 Oscillator Start-up Timer (OST) 3.2 MCLR PIC18FXX8 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin differs from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both resets and current draws outside of device specification during the RESET event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 3-2, is suggested. The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #32). This additional delay ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HS4 modes and only on Power-on Reset or wake-up from SLEEP. 3.5 PLL Lock Time-out With the PLL enabled, the time-out sequence following a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out (OST). FIGURE 3-2: RECOMMENDED MCLR CIRCUIT PIC18FXX8 3.6 Brown-out Reset (BOR) VDD R1 1 k (or greater) MCLR C1 0.1 F (not critical) A configuration bit, BOREN, can disable (if clear/ programmed), or enable (if set), the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation resets the chip. A RESET may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will then be invoked and will keep the chip in RESET an additional time delay (parameter #33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay. DS41159B-page 26 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 3.7 Time-out Sequence On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired, then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18FXX8 device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all registers. TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) PWRTEN = 0 PWRTEN = 1 Brown-out(2) Wake-up from SLEEP or Oscillator Switch Oscillator Configuration HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC EC 72 ms -- 72 ms -- External RC 72 ms -- 72 ms -- Note 1: 2 ms = Nominal time required for the 4X PLL to lock. 2: 72 ms is the nominal power-up timer delay. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-1 POR R/W-1 BOR bit 0 TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h PC + 2 0000h PC + 2(1) RCON Register 0--1 1100 0--u uuuu 0--0 uuuu 0--u uu11 0--u uu11 0--u 10uu 0--u 01uu u--u 00uu 0--1 11u0 u--u 00uu RI 1 u 0 u u u u u 1 u TO 1 u u u u 1 0 0 1 0 PD 1 u u u u 0 1 0 1 0 POR 0 u u 1 1 u u u u u BOR 0 u u 1 1 u u u 0 u STKFUL u u u u 1 u u u u u STKUNF u u u 1 u u u u u u Condition Power-on Reset MCLR Reset during normal operation Software Reset during normal operation Stack Full Reset during normal operation Stack Underflow Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from SLEEP Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2002 Microchip Technology Inc. Preliminary DS41159B-page 27 PIC18FXX8 FIGURE 3-3: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK) TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS41159B-page 28 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK) 5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TDEADTIME 0V 1V FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD VIA RC NETWORK) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2002 Microchip Technology Inc. Preliminary DS41159B-page 29 PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices TOSU PIC18F2X8 PIC18F4X8 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F2X8 PIC18F4X8 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F2X8 PIC18F4X8 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PCL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F2X8 PIC18F4X8 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F2X8 PIC18F4X8 0000 000x 0000 000u uuuu uuuu(1) INTCON2 PIC18F2X8 PIC18F4X8 111- -1-1 111- -1-1 uuuu -u-u(1) INTCON3 PIC18F2X8 PIC18F4X8 11-- 0-00 11-- 0-00 uu-u u-uu(1) INDF0 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC0 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC0 PIC18F2X8 PIC18F4X8 N/A N/A N/A PREINC0 PIC18F2X8 PIC18F4X8 N/A N/A N/A PLUSW0 PIC18F2X8 PIC18F4X8 N/A N/A N/A FSR0H PIC18F2X8 PIC18F4X8 ---- 0000 ---- 0000 ---- uuuu FSR0L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC1 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC1 PIC18F2X8 PIC18F4X8 N/A N/A N/A PREINC1 PIC18F2X8 PIC18F4X8 N/A N/A N/A PLUSW1 PIC18F2X8 PIC18F4X8 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). DS41159B-page 30 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices FSR1H PIC18F2X8 PIC18F4X8 ---- 0000 ---- 0000 ---- uuuu FSR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2X8 PIC18F4X8 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A PREINC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A PLUSW2 PIC18F2X8 PIC18F4X8 N/A N/A N/A FSR2H PIC18F2X8 PIC18F4X8 ---- 0000 ---- 0000 ---- uuuu FSR2L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F2X8 PIC18F4X8 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TMR0L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F2X8 PIC18F4X8 ---- ---0 ---- ---0 ---- ---u LVDCON PIC18F2X8 PIC18F4X8 --00 0101 --00 0101 --uu uuuu WDTCON PIC18F2X8 PIC18F4X8 ---- ---0 ---- ---0 ---- ---u PIC18F2X8 PIC18F4X8 0--1 11q0 0--1 qquu u--u qquu RCON(4) TMR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F2X8 PIC18F4X8 0-00 0000 u-uu uuuu u-uu uuuu TMR2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PR2 PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 1111 1111 T2CON PIC18F2X8 PIC18F4X8 -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). 2002 Microchip Technology Inc. Preliminary DS41159B-page 31 PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices ADRESH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F2X8 PIC18F4X8 0000 00-0 0000 00-0 uuuu uu-u ADCON1 PIC18F2X8 PIC18F4X8 00-- 0000 00-- 0000 uu-- uuuu CCPR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2X8 PIC18F4X8 --00 0000 --00 0000 --uu uuuu PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ECCPR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ECCPR1L PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 0000 0000 ECCP1CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 0000 0000 ECCP1DEL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 0000 0000 ECCPAS PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu CVRCON CMCON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TMR3H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F2X8 PIC18F4X8 0000 0000 uuuu uuuu uuuu uuuu SPBRG PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RCREG PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXREG PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXSTA PIC18F2X8 PIC18F4X8 0000 -01x 0000 -01u uuuu -uuu RCSTA PIC18F2X8 PIC18F4X8 0000 000x 0000 000u uuuu uuuu EEADR PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu EEDATA PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu EECON2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu EECON1 PIC18F2X8 PIC18F4X8 xx-0 x000 uu-0 u000 uu-0 u000 IPR3 PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PIE3 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). DS41159B-page 32 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices IPR2 PIC18F2X8 PIC18F4X8 -1-1 1111 -1-1 1111 -u-u uuuu PIR2 PIC18F2X8 PIC18F4X8 -0-0 0000 -0-0 0000 -u-u uuuu(1) PIE2 PIC18F2X8 PIC18F4X8 -0-0 0000 -0-0 0000 -u-u uuuu IPR1 PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(1) PIE1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PIC18F2X8 PIC18F4X8 0000 -111 0000 -111 uuuu -uuu TRISE TRISD PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu PIC18F2X8 PIC18F4X8 -111 1111(5) -111 1111(5) -uuu uuuu(5) TRISA(5) LATE PIC18F2X8 PIC18F4X8 ---- -xxx ---- -uuu ---- -uuu PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu LATD LATC PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu (5) (5) (5) PIC18F2X8 PIC18F4X8 -xxx xxxx -uuu uuuu -uuu uuuu(5) LATA PORTE PIC18F2X8 PIC18F4X8 ---- -xxx ---- -000 ---- -uuu PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PORTD PORTC PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PIC18F2X8 PIC18F4X8 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) PORTA(5) TXERRCNT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu RXERRCNT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu COMSTAT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu CIOCON PIC18F2X8 PIC18F4X8 1000 ---1000 ---uuuu ---BRGCON3 PIC18F2X8 PIC18F4X8 -0-- -000 -0-- -000 -u-- -uuu BRGCON2 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu BRGCON1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu CANCON PIC18F2X8 PIC18F4X8 xxxx xxxuuuu uuuuuuu uuuPIC18F2X8 PIC18F4X8 xxx- xxxuuu- uuuuuu- uuuCANSTAT(6) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). 2002 Microchip Technology Inc. Preliminary DS41159B-page 33 PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices RXB0D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC PIC18F2X8 PIC18F4X8 0xxx xxxx 0uuu uuuu uuuu uuuu RXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL PIC18F2X8 PIC18F4X8 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON PIC18F2X8 PIC18F4X8 000- 0000 000- 0000 uuu- uuuu RXB1D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC PIC18F2X8 PIC18F4X8 0xxx xxxx 0uuu uuuu uuuu uuuu RXB1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL PIC18F2X8 PIC18F4X8 xxxx x0xx uuuu u0uu uuuu uuuu RXB1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TXB0D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). DS41159B-page 34 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices TXB0DLC PIC18F2X8 PIC18F4X8 0x00 xxxx 0u00 uuuu uuuu uuuu TXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0SIDL PIC18F2X8 PIC18F4X8 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TXB1D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC PIC18F2X8 PIC18F4X8 0x00 xxxx 0u00 uuuu uuuu uuuu TXB1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL PIC18F2X8 PIC18F4X8 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TXB2D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2DLC PIC18F2X8 PIC18F4X8 0x00 xxxx 0u00 uuuu uuuu uuuu TXB2EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL PIC18F2X8 PIC18F4X8 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB2SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). 2002 Microchip Technology Inc. Preliminary DS41159B-page 35 PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices RXM1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM1SIDL PIC18F2X8 PIC18F4X8 xxx- --xx uuu- --uu uuu- --uu RXM1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL PIC18F2X8 PIC18F4X8 xxx- --xx uuu- --uu uuu- --uu RXM0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF3SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read '0'. 6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4). DS41159B-page 36 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 4.0 MEMORY ORGANIZATION There are three memory blocks in Enhanced MCU devices. These memory blocks are: * Enhanced FLASH Program Memory * Data Memory * EEPROM Data Memory Data and program memory use separate busses, which allows concurrent access of these blocks. Additional detailed information on Data EEPROM and FLASH program memory is provided in Section 5.0 and Section 6.0, respectively. Figure 4-1 shows the diagram for program memory map and stack for the PIC18F258 and PIC18F458. Figure 4-2 shows the the diagram for the program memory map and stack for the PIC18F248 and PIC18F448. 4.1.1 INTERNAL PROGRAM MEMORY OPERATION 4.1 Program Memory Organization The PIC18F258/458 devices have a 21-bit program counter that is capable of addressing a 2 Mbyte program memory space. The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The PIC18F258 and the PIC18F458 have 32 Kbytes of internal Enhanced FLASH program memory. This means that the PIC18F258 and the PIC18F458 can store up to 16K of single word instructions. The PIC18F248 and PIC18F448 have 16 Kbytes of Enhanced FLASH program memory. This translates into 8192 single-word instructions, which can be stored in the Program memory. Accessing a location between the physically implemented memory and the 2 Mbyte address will cause a read of all '0's (a NOP instruction). FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F258/458 FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR PIC18F248/448 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 * * * PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 * * * Stack Level 31 RESET Vector 0000h Stack Level 31 RESET Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h User Memory Space User Memory Space 1FFFFFh 200000h DS41159B-page 37 On-Chip Program Memory 7FFFh 8000h Read '0' Read '0' 1FFFFFh 200000h 2002 Microchip Technology Inc. Preliminary PIC18FXX8 4.2 Return Address Stack 4.2.2 The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a PUSH, CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the return instructions. The stack operates as a 31-word by 21-bit stack memory and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all RESETS. There is no RAM associated with stack pointer 00000b. This is only a RESET value. During a CALL type instruction causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC. During a RETURN type instruction causing a pop from the stack, the contents of the RAM location indicated by the STKPTR is transferred to the PC and then the stack pointer is decremented. The stack space is not part of either program or data space. The stack pointer is readable and writable, and the data on the top of the stack is readable and writable through SFR registers. Status bits indicate if the stack pointer is at or beyond the 31 levels provided. RETURN STACK POINTER (STKPTR) The STKPTR register contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. Register 4-1 shows the STKPTR register. The value of the stack pointer can be 0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when values are popped off the stack. At RESET, the stack pointer value will be 0. The user may read and write the stack pointer value. This feature can be used by a Real Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit can only be cleared in software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. Refer to Section 21.0 for a description of the device configuration bits. If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer will be set to 0. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. The 32nd push will overwrite the 31st push (and so on), while STKPTR remains at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at 0. The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appropriate actions can be taken. 4.2.1 TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL allow access to the contents of the stack location indicated by the STKPTR register. This allows users to implement a software stack, if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user should disable the global interrupt enable bits during this time to prevent inadvertent stack operations. DS41159B-page 38 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 4-1: STKPTR - STACK POINTER REGISTER R/C-0 STKFUL bit 7 bit 7 R/C-0 STKUNF U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as '0' bit 6 bit 5 bit 4-0 SP4:SP0: Stack Pointer Location bits Note: Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared C = Clearable bit Bit 7 and bit 6 need to be cleared following a stack underflow or a stack overflow. FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 001A34h 000D58h 000000h STKPTR<4:0> 00010 00011 00010 00001 00000(1) Note 1: No RAM associated with this address; always maintained `0's. 2002 Microchip Technology Inc. Preliminary DS41159B-page 39 PIC18FXX8 4.2.3 PUSH AND POP INSTRUCTIONS EXAMPLE 4-1: CALL SUB1, FAST Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place a return address on the stack. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK * * SUB1 * * * RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 4.2.4 STACK FULL/UNDERFLOW RESETS 4.4 PCL, PCLATH and PCLATU These RESETS are enabled by programming the STVREN configuration bit. When the STVREN bit is disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device RESET. When the STVREN bit is enabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR. 4.3 Fast Register Stack The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSb of PCL is fixed to a value of '0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 4.8.1). A "fast return" option is available for interrupts and calls. A fast register stack is provided for the STATUS, WREG and BSR registers and is only one layer in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the fast register stack are then loaded back into the working registers if the fast return instruction is used to return from the interrupt. A low or high priority interrupt source will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a fast call instruction must be executed. Example 4-1 shows a source code example that uses the fast register stack. DS41159B-page 40 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 4.5 Clocking Scheme/Instruction Cycle instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-4. The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the FIGURE 4-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC Mode) Internal Phase Clock PC Fetch INST (PC) Execute INST (PC-2) PC+2 PC+4 Fetch INST (PC+2) Execute INST (PC) Fetch INST (PC+4) Execute INST (PC+2) 4.6 Instruction Flow/Pipelining 4.7 Instructions in Program Memory An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), two cycles are required to complete the instruction (Example 4-2). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = '0'). Figure 4-3 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read '0' (see Section 4.4). The CALL and GOTO instructions have an absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Example 4-3 shows how the instruction "GOTO 000006h" is encoded in the program memory. Program branch instructions that encode a relative address offset operate in the same manner. The offset value stored in a branch instruction represents the number of single word instructions by which the PC will be offset. Section 25.0 provides further details of the instruction set. 2002 Microchip Technology Inc. Preliminary DS41159B-page 41 PIC18FXX8 EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 1. MOVLW 55h 2. MOVWF PORTB 3. BRA SUB_1 4. BSF PORTA, BIT3 (Forced NOP) TCY1 Execute 1 Fetch 2 TCY2 Execute 2 Fetch 3 TCY3 TCY4 TCY5 Fetch 1 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. EXAMPLE 4-3: INSTRUCTIONS IN PROGRAM MEMORY Opcode 0E55h EF03h, F000h Memory 55h 0Eh 03h EFh 00h F0h Address 000007h 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h 000011h 000012h Instruction -- MOVLW 055h GOTO 000006h MOVFF 123h, 456h C123h, F456h 23h C1h 56h F4h -- DS41159B-page 42 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 4.7.1 TWO-WORD INSTRUCTIONS The PIC18FXX8 devices have 4 two-word instructions: MOVFF, CALL, GOTO and LFSR. The 4 Most Significant bits of the second word are set to `1's, and indicate a special NOP instruction. The lower 12 bits of the second word contain the data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that changes the PC. A program example that demonstrates this concept is shown in Example 4-4. Refer to Section 25.0 for further details of the instruction set. A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Warning: The LSb of PCL is fixed to a value of `0'. Hence, computed GOTO to an odd address is not possible. 4.8 Lookup Tables Lookup tables are implemented two ways. These are: * Computed GOTO * Table Reads 4.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Lookup table data may be stored as 2 bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to, program memory. Data is transferred to/from program memory, one byte at a time. A description of the Table Read/Table Write operation is shown in Section 6.1. 4.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). The ADDWF PCL instruction does not update PCLATH/ PCLATU. A read operation on PCL must be performed prior to the ADDWF PCL. EXAMPLE 4-4: CASE 1: Object Code TWO-WORD INSTRUCTIONS Source Code TSTFSZ MOVFF REG1 ; is RAM location 0? 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 REG1, REG2 ; No, execute 2-word instruction ; 2nd operand holds address of REG2 ADDWF REG3 ; continue code Source Code TSTFSZ MOVFF REG1 ; is RAM location 0? REG1, REG2 ; Yes ; 2nd operand becomes NOP ADDWF REG3 ; continue code 2002 Microchip Technology Inc. Preliminary DS41159B-page 43 PIC18FXX8 4.9 Data Memory Organization 4.9.1 The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-6 shows the data memory organization for the PIC18FXX8 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPR's are used for data storage and scratch pad operations in the user's application. The SFR's start at the last location of Bank 15 (FFFh) and grow downwards. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as '0's. The entire data memory may be accessed directly, or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of the File Select Register (FSR). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction, that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 provides a detailed description of the Access RAM. GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly. Indirect addressing operates through the File Select Registers (FSR). The operation of indirect addressing is shown in Section 4.12. Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other RESETS. Data RAM is available for use as GPR registers by all instructions. Bank 15 (F00h to FFFh) contains SFRs. All other banks of data memory contain GPR registers, starting with bank 0. 4.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 4-1. The SFRs can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as '0's. See Table 4-1 for addresses for the SFRs. DS41159B-page 44 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 4-5: BSR<3:0> = 0000 00h Bank 0 FFh 00h Bank 1 FFh 00h GPR FFh 300h DATA MEMORY MAP FOR PIC18F248/448 Data Memory Map Access RAM GPR GPR 1FFh 200h 000h 05Fh 060h 0FFh 100h = 0001 Access Bank Access RAM = 0010 = 1110 Bank 2 to Bank 14 Unused Read '00h' SFR 00h 5Fh 60h FFh When a = 0, the BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). The next 160 bytes are Special Function Registers (from Bank 15). EFFh F00h F5Fh F60h FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. = 1111 00h Bank 15 FFh Unused SFR 2002 Microchip Technology Inc. Preliminary DS41159B-page 45 PIC18FXX8 FIGURE 4-6: BSR<3:0> = 0000 00h Bank 0 FFh 00h Bank 1 FFh 00h Bank 2 = 0011 FFh 00h Bank 3 FFh = 0100 Bank 4 00h Bank 5 FFh GPR 5FFh 600h GPR 4FFh 500h GPR 3FFh 400h Access Bank 00h Access Bank low 5Fh (GPR) 60h Access Bank high FFh (SFR) DATA MEMORY MAP FOR PIC18F258/458 Data Memory Map Access RAM GPR GPR 1FFh 200h GPR 2FFh 300h 000h 05Fh 060h 0FFh 100h = 0001 = 0010 = 0101 = 0110 = 1110 Bank 6 to Bank 14 Unused Read `00h' When a = 0, the BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). = 1111 00h Bank 15 FFh SFR SFR EFFh F00h F5Fh F60h FFFh The next 160 bytes are Special Function Registers (from Bank 15). When a = 1, the BSR is used to specify the RAM location that the instruction uses. DS41159B-page 46 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 4-1: Address SPECIAL FUNCTION REGISTER MAP Name Address FDFh Name INDF2(2) Address Name Address Name FFFh TOSU FFEh TOSH FFDh TOSL FFCh STKPTR FFBh PCLATU FFAh PCLATH FF9h PCL FF8h TBLPTRU FF7h TBLPTRH FF6h TBLPTRL FF5h TABLAT FF4h PRODH FF3h PRODL FF2h INTCON FF1h INTCON2 FF0h INTCON3 FEFh INDF0(2) FEEh POSTINC0(2) FEDh POSTDEC0 FECh PREINC0(2) FEBh PLUSW0(2) FEAh FSR0H FE9h FSR0L FE8h WREG FE7h INDF1 (2) (2) FBFh CCPR1H FBEh CCPR1L FBDh CCP1CON FBCh ECCPR1H(5) FBBh ECCPR1L FB9h FB8h -- -- (5) F9Fh IPR1 F9Eh PIR1 F9Dh PIE1 F9Ch F9Bh F9Ah F99h F98h F97h -- -- -- -- -- -- FDEh POSTINC2(2) FDDh POSTDEC2(2) FDCh PREINC2(2) FDBh PLUSW2 FDAh FSR2H FD9h FSR2L FD8h STATUS FD7h TMR0H FD6h TMR0L FD5h T0CON FD4h -- FD3h OSCCON FD2h LVDCON FD1h WDTCON FD0h RCON FCFh TMR1H FCEh TMR1L FCDh T1CON FCCh TMR2 FCBh PR2 FCAh T2CON FC9h SSPBUF FC8h SSPADD FC7h SSPSTAT FC6h SSPCON1 FC5h SSPCON2 FC4h ADRESH FC3h ADRESL FC2h ADCON0 FC1h ADCON1 FC0h -- (2) FBAh ECCP1CON(5) FB7h ECCP1DEL(5) FB6h ECCPAS(5) FB5h CVRCON(5) FB4h CMCON FB3h TMR3H FB2h TMR3L FB1h T3CON FB0h -- FAFh SPBRG FAEh RCREG FADh TXREG FACh TXSTA FABh RCSTA FAAh -- FA9h EEADR FA8h EEDATA FA7h EECON2 FA6h EECON1 FA5h IPR3 FA4h PIR3 FA3h PIE3 FA2h IPR2 FA1h PIR2 FA0h PIE2 (5) F96h TRISE(5) F95h TRISD(5) F94h TRISC F93h TRISB F92h TRISA F91h F90h F8Fh F8Eh -- -- -- -- F8Dh LATE(5) F8Ch LATD(5) F8Bh LATC F8Ah LATB F89h LATA F88h F87h F86h F85h -- -- -- -- FE6h POSTINC1(2) FE5h POSTDEC1(2) FE4h PREINC1(2) FE3h PLUSW1(2) FE2h FSR1H FE1h FSR1L FE0h BSR F84h PORTE(5) F83h PORTD(5) F82h PORTC F81h PORTB F80h PORTA Note 1: Unimplemented registers are read as '0'. 2: This is not a physical register. 3: Contents of register are dependent on WIN2:WIN0 bits in CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register, due to the Microchip Header file requirement. 5: These registers are not implemented on the PIC18F248 and PIC18F258. 2002 Microchip Technology Inc. Preliminary DS41159B-page 47 PIC18FXX8 TABLE 4-1: Address F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h SPECIAL FUNCTION REGISTER MAP (CONTINUED) Name -- -- -- -- -- -- -- -- -- Address F5Fh Name -- Address F3Fh Name -- Address Name F1Fh RXM1EIDL F1Eh RXM1EIDH F1Dh RXM1SIDL F1Ch RXM1SIDH F1Bh RXM0EIDL F1Ah RXM0EIDH F19h RXM0SIDL F18h RXM0SIDH F17h RXF5EIDL F16h RXF5EIDH F15h RXF5SIDL F14h RXF5SIDH F13h RXF4EIDL F12h RXF4EIDH F11h RXF4SIDL F10h RXF4SIDH F0Fh RXF3EIDL F0Eh RXF3EIDH F0Dh RXF3SIDL F0Ch RXF3SIDH F0Bh RXF2EIDL F0Ah RXF2EIDH F09h RXF2SIDL F08h RXF2SIDH F07h RXF1EIDL F06h RXF1EIDH F05h RXF1SIDL F04h RXF1SIDH F03h RXF0EIDL F02h RXF0EIDH F01h RXF0SIDL F00h RXF0SIDH F5Eh CANSTATRO1(4) F5Dh RXB1D7 F5Ch RXB1D6 F5Bh RXB1D5 F5Ah RXB1D4 F59h RXB1D3 F58h RXB1D2 F57h RXB1D1 F56h RXB1D0 F55h RXB1DLC F54h RXB1EIDL F53h RXB1EIDH F52h RXB1SIDL F51h RXB1SIDH F50h RXB1CON F4Fh -- F4Eh CANSTATRO2(4) F4Dh TXB0D7 F4Ch TXB0D6 F4Bh TXB0D5 F4Ah TXB0D4 F49h TXB0D3 F48h TXB0D2 F47h TXB0D1 F46h TXB0D0 F45h TXB0DLC F44h TXB0EIDL F43h TXB0EIDH F42h TXB0SIDL F41h TXB0SIDH F40h TXB0CON F3Eh CANSTATRO3(4) F3Dh TXB1D7 F3Ch TXB1D6 F3Bh TXB1D5 F3Ah TXB1D4 F39h TXB1D3 F38h TXB1D2 F37h TXB1D1 F36h TXB1D0 F35h TXB1DLC F34h TXB1EIDL F33h TXB1EIDH F32h TXB1SIDL F31h TXB1SIDH F30h TXB1CON F2Fh -- F2Eh CANSTATRO4(4) F2Dh TXB2D7 F2Ch TXB2D6 F2Bh TXB2D5 F2Ah TXB2D4 F29h TXB2D3 F28h TXB2D2 F27h TXB2D1 F26h TXB2D0 F25h TXB2DLC F24h TXB2EIDL F23h TXB2EIDH F22h TXB2SIDL F21h TXB2SIDH F20h TXB2CON F76h TXERRCNT F75h RXERRCNT F74h COMSTAT F73h CIOCON F72h BRGCON3 F71h BRGCON2 F70h BRGCON1 F6Fh CANCON F6Eh CANSTAT F6Dh RXB0D7(3) F6Ch RXB0D6(3) F6Bh RXB0D5(3) (3) F6Ah RXB0D4(3) F69h RXB0D3 F67h F65h F68h RXB0D2(3) RXB0D1(3) RXB0DLC(3) (3) F66h RXB0D0(3) F64h RXB0EIDL(3) F63h RXB0EIDH F61h F62h RXB0SIDL(3) RXB0SIDH(3) F60h RXB0CON(3) Note: Shaded registers are available in Bank 15, while the rest are in Access Bank low. Note 1: Unimplemented registers are read as '0'. 2: This is not a physical register. 3: Contents of register are dependent on WIN2:WIN0 bits in CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register, due to the Microchip Header file requirement. 5: These registers are not implemented on the PIC18F248 and PIC18F258. DS41159B-page 48 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 4-2: File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON REGISTER FILE SUMMARY Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR Page: ---0 0000 0000 0000 0000 0000 Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 ---0 0000 0000 0000 0000 0000 bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 -- INT0IE -- INT2IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 111- -1-1 11-1 0-00 n/a n/a n/a n/a n/a ---- xxxx xxxx xxxx uuuu uuuu n/a n/a n/a n/a n/a ---- xxxx xxxx xxxx Bank Select Register ---- 0000 n/a n/a n/a n/a n/a ---- xxxx xxxx xxxx OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS -- IRVST -- -- T0SE -- LVDEN -- RI PSA -- LVDL3 -- TO T0PS2 -- LVDL2 -- PD T0PS1 -- LVDL1 -- POR T0PS0 SCS LVDL0 BOR 1111 1111 ---- ---0 --00 0101 30, 38 30, 38 30, 38 30, 39 30, 40 30, 40 30, 40 30, 68 30, 68 30, 68 30, 68 30, 75 30, 75 30, 79 30, 80 30, 81 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 30, 55 31, 55 31, 55 31, 54 31, 55 31, 55 31, 55 31, 55 31, 55 31, 55 31, 55 31, 57 31, 109 31, 109 31, 107 31, 20 31, 257 31, 268 Top-of-Stack Upper Byte (TOS<20:16>) Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- bit21(2) Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register) -- Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 1 High Indirect Data Memory Address Pointer 1 Low Byte Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) -- -- -- -- -- -- -- N Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte Timer0 Register High Byte Timer0 Register Low Byte TMR0ON -- -- -- IPEN T08BIT -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 0 High Indirect Data Memory Address Pointer 0 Low Byte SWDTEN ---- ---0 0--1 11qq 31, 58, 91 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as '0's. 2: Bit21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read `0' in all other Oscillator modes. 2002 Microchip Technology Inc. Preliminary DS41159B-page 49 PIC18FXX8 TABLE 4-2: File Name TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 CCPR1H CCPR1L CCP1CON ECCPR1H(1) ECCPR1L(1) ECCP1DEL(1) ECCPAS(1) CVRCON(1) CMCON TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA EEADR EEDATA EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 (1) REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR Page: xxxx xxxx xxxx xxxx T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 0000 0000 1111 1111 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx 0000 0000 BF SSPM0 SEN P CKP ACKEN S SSPM3 RCEN R/W SSPM2 PEN UA SSPM1 RSEN 31, 113 31, 113 31, 111 31, 116 31, 116 31, 115 31, 144 31, 150 Timer1 Register High Byte Timer1 Register Low Byte RD16 Timer2 Register Timer2 Period Register -- TOUTPS3 SSP Receive Buffer/Transmit Register SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. SMP WCOL GCEN CKE SSPOV ACKSTAT D/A SSPEN ACKDT -- 0000 0000 31, 142, 151 0000 0000 31, 143, 152 0000 0000 xxxx xxxx xxxx xxxx 31, 153 32, 239 32, 239 32, 237 32, 238 32, 122 32, 122 32, 121 32, 131 32, 131 32, 129 32, 138 32, 140 32, 251 32, 245 32, 119 32, 119 32, 117 32, 183 32, 189 32, 187 32, 181 32, 182 32, 59 32, 59 32, 59 32, 90 32, 84 32, 87 33, 89 33, 83 33, 86 A/D Result Register High Byte A/D Result Register Low Byte ADCS1 ADFM ADCS0 ADCS2 CHS2 -- CHS1 -- CHS0 PCFG3 GO/DONE PCFG2 -- PCFG1 ADON PCFG0 0000 00-0 00-- 0000 xxxx xxxx xxxx xxxx Capture/Compare/PWM Register1 High Byte Capture/Compare/PWM Register1 Low Byte -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 Enhanced Capture/Compare/PWM Register1 High Byte Enhanced Capture/Compare/PWM Register1 Low Byte EDC1B1 EPDC5 ECCPAS1 CVRR C2INV EDC1B0 EPDC4 ECCPAS0 CVRSS C1INV CCP1M0 --00 0000 xxxx xxxx xxxx xxxx ECCP1CON(1) EPWM1M1 EPWM1M0 EPDC7 ECCPASE CVREN C2OUT EPDC6 ECCPAS2 CVROE C1OUT ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 EPDC3 PSSAC1 CVR3 CIS EPDC2 PSSAC0 CVR2 CM2 EPDC1 PSSBD1 CVR1 CM1 EPDC0 0000 0000 PSSBD0 0000 0000 CVR0 CM0 0000 0000 0000 0000 xxxx xxxx xxxx xxxx Timer3 Register High Byte Timer3 Register Low Byte RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS USART1 Baud Rate Generator USART1 Receive Register USART1 Transmit Register CSRC SPEN TX9 RX9 TXEN SREN SYNC CREN -- ADDEN BRGH FERR TRMT OERR TX9D RX9D TMR3ON 0000 0000 0000 0000 0000 0000 0000 0000 0000 -010 0000 000X xxxx xxxx xxxx xxxx xxxx xxxx EEPROM Address Register EEPROM Data Register EEPROM Control Register2 (not a physical register) EEPGD IRXIP IRXIF IRXIE -- -- -- CFGS WAKIP WAKIF WAKIE CMIP CMIF CMIE -- ERRIP ERRIF ERRIE -- -- -- FREE TXB2IP TXB2IF TXB2IE EEIP EEIF EEIE WRERR TXB1IP TXB1IF TXB1IE BCLIP BCLIF BCLIE WREN TXB0IP TXB0IF TXB0IE LVDIP LVDIF LVDIE WR RXB1IP RXB1IF RXB1IE TMR3IF RD RXB0IP RXB0IF RXB0IE xx-0 x000 32, 60, 67 1111 1111 0000 0000 0000 0000 TMR3IP ECCP1IP(1) -1-1 1111 ECCP1IF(1) -0-0 0000 TMR3IE ECCP1IE(1) -0-0 0000 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as '0's. 2: Bit21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read `0' in all other Oscillator modes. DS41159B-page 50 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 4-2: File Name IPR1 PIR1 PIE1 TRISE(1) TRISD(1) TRISC TRISB TRISA (3) REGISTER FILE SUMMARY (CONTINUED) Bit 7 PSPIP PSPIF PSPIE IBF Bit 6 ADIP ADIF ADIE OBF Bit 5 RCIP RCIF RCIE IBOV Bit 4 TXIP TXIF TXIE PSPMODE Bit 3 SSPIP SSPIF SSPIE -- Bit 2 CCP1IP CCP1IF CCP1IE Bit 1 TMR2IP TMR2IF TMR2IE Bit 0 TMR1IP TMR1IF TMR1IE Value on Details on POR, BOR Page: 1111 1111 0000 0000 0000 0000 0000 -111 1111 1111 1111 1111 1111 1111 --11 1111 -- Read PORTE Data Latch, Write PORTE Data Latch(1) ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx Read PORTE pins, Write PORTE Data Latch(1) ---- -000 xxxx xxxx xxxx xxxx xxxx xxxx -x0x 0000 TEC3 REC3 RXBP -- -- SEG1PH0 BRP3 WIN2 ICODE2 RXB0D73 RXB0D63 RXB0D53 RXB0D43 RXB0D33 RXB0D23 RXB0D13 RXB0D03 DLC3 EID3 EID11 EXID SID6 TEC2 REC2 TXWARN -- PRSEG2 BRP2 WIN1 ICODE1 RXB0D72 RXB0D62 RXB0D52 RXB0D42 RXB0D32 RXB0D22 RXB0D12 RXB0D02 DLC2 EID2 EID10 -- SID5 TEC1 REC1 RXWARN -- PRSEG1 BRP1 WIN0 ICODE0 TEC0 REC0 EWARN -- 0000 0000 0000 0000 0000 0000 --00 ---TEC4 REC4 TXBP CANCAP -- SEG1PH1 BRP4 ABAT -- RXB0D74 RXB0D64 RXB0D54 RXB0D44 RXB0D34 RXB0D24 RXB0D14 RXB0D04 RB0 EID4 EID12 SRR SID7 -- -- 33, 88 33, 82 33, 85 33, 103 33, 100 33, 98 33, 95 33, 93 33, 102 33, 100 33, 98 33, 95 33, 93 33, 102 33, 100 33, 98 33, 95 33, 93 33, 207 33, 212 33, 203 33, 217 33, 217 33, 216 33, 215 33, 199 33, 200 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 210 34, 210 34, 210 34, 209 34, 208 Data Direction bits for PORTE(1) Data Direction Control Register for PORTD(1) Data Direction Control Register for PORTC Data Direction Control Register for PORTB -- -- Data Direction Control Register for PORTA -- -- LATE(1) LATD(1) LATC LATB LATA(3) PORTE(1) PORTD(1) PORTC PORTB PORTA(3) TXERRCNT RXERRCNT COMSTAT CIOCON BRGCON3 BRGCON2 BRGCON1 CANCON CANSTAT RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON Read PORTD Data Latch, Write PORTD Data Latch(1) Read PORTC Data Latch, Write PORTC Data Latch Read PORTB Data Latch, Write PORTB Data Latch -- -- Read PORTA Data Latch, Write PORTA Data Latch -- -- -- -- Read PORTD pins, Write PORTD Data Latch(1) Read PORTC pins, Write PORTC Data Latch Read PORTB pins, Write PORTB Data Latch -- TEC7 REC7 -- -- SEG2PHTS SJW1 REQOP2 RXB0D77 RXB0D67 RXB0D57 RXB0D47 RXB0D37 RXB0D27 RXB0D17 RXB0D07 -- EID7 EID15 SID2 SID10 RXFUL Read PORTA pins, Write PORTA Data Latch TEC6 REC6 -- WAKFIL SAM SJW0 REQOP1 RXB0D76 RXB0D66 RXB0D56 RXB0D46 RXB0D36 RXB0D26 RXB0D16 RXB0D06 RXRTR EID6 EID14 SID1 SID9 RXM1 TEC5 REC5 TXBO ENDRHI -- SEG1PH2 BRP5 REQOP0 RXB0D75 RXB0D65 RXB0D55 RXB0D45 RXB0D35 RXB0D25 RXB0D15 RXB0D05 RB1 EID5 EID13 SID0 SID8 RXM0 RXB0OVFL RXB1OVFL SEG2PH2 SEG2PH1 SEG2PH0 -0-- -000 PRSEG0 0000 0000 BRP0 -- -- 0000 0000 xxxx xxxxxx- xxx- OPMODE2 OPMODE1 OPMODE0 RXB0D71 RXB0D70 xxxx xxxx RXB0D61 RXB0D60 xxxx xxxx RXB0D51 RXB0D50 xxxx xxxx RXB0D41 RXB0D40 xxxx xxxx RXB0D31 RXB0D30 xxxx xxxx RXB0D21 RXB0D20 xxxx xxxx RXB0D11 RXB0D10 xxxx xxxx RXB0D01 RXB0D00 xxxx xxxx DLC1 EID1 EID9 EID17 SID4 JTOFF DLC0 EID0 EID8 EID16 SID3 FILHIT0 -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 000- 0000 RXRTRRO RXB0DBEN Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as '0's. 2: Bit21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read `0' in all other Oscillator modes. 2002 Microchip Technology Inc. Preliminary DS41159B-page 51 PIC18FXX8 TABLE 4-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 -- RXB1D74 RXB1D64 RXB1D54 RXB1D44 RXB1D34 RXB1D24 RXB1D14 RXB1D04 RB0 EID4 EID12 SRR SID7 -- -- TXB0D74 TXB0D64 TXB0D54 TXB0D44 TXB0D34 TXB0D24 TXB0D14 TXB0D04 -- EID4 EID12 -- SID7 TXERR -- TXB1D74 TXB1D64 TXB1D54 TXB1D44 TXB1D34 TXB1D24 TXB1D14 TXB1D04 -- EID4 EID12 -- SID7 TXERR Bit 3 ICODE2 RXB1D73 RXB1D63 RXB1D53 RXB1D43 RXB1D33 RXB1D23 RXB1D13 RXB1D03 DLC3 EID3 EID11 EXID SID6 RXRTRRO ICODE2 TXB0D73 TXB0D63 TXB0D53 TXB0D43 TXB0D33 TXB0D23 TXB0D13 TXB0D03 DLC3 EID3 EID11 EXIDE SID6 TXREQ ICODE2 TXB1D73 TXB1D63 TXB1D53 TXB1D43 TXB1D33 TXB1D23 TXB1D13 TXB1D03 DLC3 EID3 EID11 EXIDE SID6 TXREQ Bit 2 ICODE1 RXB1D72 RXB1D62 RXB1D52 RXB1D42 RXB1D32 RXB1D22 RXB1D12 RXB1D02 DLC2 EID2 EID10 -- SID5 FILHIT2 ICODE1 TXB0D72 TXB0D62 TXB0D52 TXB0D42 TXB0D32 TXB0D22 TXB0D12 TXB0D02 DLC2 EID2 EID10 -- SID5 -- ICODE1 TXB1D72 TXB1D62 TXB1D52 TXB1D42 TXB1D32 TXB1D22 TXB1D12 TXB1D02 DLC2 EID2 EID10 -- SID5 -- Bit 1 ICODE0 Bit 0 -- Value on Details on POR, BOR Page: xxx- xxx33, 200 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 211 34, 210 34, 210 34, 210 34, 209 34, 209 33, 200 34, 206 34, 206 34, 206 34, 206 34, 206 34, 206 34, 206 34, 206 35, 207 35, 206 35, 205 35, 205 35, 205 35, 204 33, 200 35, 206 35, 206 35, 206 35, 206 35, 206 35, 206 35, 206 35, 206 35, 207 35, 206 35, 205 35, 205 35, 205 35, 204 CANSTATRO1 OPMODE2 OPMODE1 OPMODE0 RXB1D7 RXB1D6 RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON TXB0D7 TXB0D6 TXB0D5 TXB0D4 TXB0D3 TXB0D2 TXB0D1 TXB0D0 TXB0DLC TXB0EIDL TXB0EIDH TXB0SIDL TXB0SIDH TXB0CON TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH TXB1SIDL TXB1SIDH TXB1CON RXB1D77 RXB1D67 RXB1D57 RXB1D47 RXB1D37 RXB1D27 RXB1D17 RXB1D07 -- EID7 EID15 SID2 SID10 RXFUL TXB0D77 TXB0D67 TXB0D57 TXB0D47 TXB0D37 TXB0D27 TXB0D17 TXB0D07 -- EID7 EID15 SID2 SID10 -- TXB1D77 TXB1D67 TXB1D57 TXB1D47 TXB1D37 TXB1D27 TXB1D17 TXB1D07 -- EID7 EID15 SID2 SID10 -- RXB1D76 RXB1D66 RXB1D56 RXB1D46 RXB1D36 RXB1D26 RXB1D16 RXB1D06 RXRTR EID6 EID14 SID1 SID9 RXM1 TXB0D76 TXB0D66 TXB0D56 TXB0D46 TXB0D36 TXB0D26 TXB0D16 TXB0D06 TXRTR EID6 EID14 SID1 SID9 TXABT TXB1D76 TXB1D66 TXB1D56 TXB1D46 TXB1D36 TXB1D26 TXB1D16 TXB1D06 TXRTR EID6 EID14 SID1 SID9 TXABT RXB1D75 RXB1D65 RXB1D55 RXB1D45 RXB1D35 RXB1D25 RXB1D15 RXB1D05 RB1 EID5 EID13 SID0 SID8 RXM0 TXB0D75 TXB0D65 TXB0D55 TXB0D45 TXB0D35 TXB0D25 TXB0D15 TXB0D05 -- EID5 EID13 SID0 SID8 TXLARB TXB1D75 TXB1D65 TXB1D55 TXB1D45 TXB1D35 TXB1D25 TXB1D15 TXB1D05 -- EID5 EID13 SID0 SID8 TXLARB RXB1D71 RXB1D70 xxxx xxxx RXB1D61 RXB1D60 xxxx xxxx RXB1D51 RXB1D50 xxxx xxxx RXB1D41 RXB1D40 xxxx xxxx RXB1D31 RXB1D30 xxxx xxxx RXB1D21 RXB1D20 xxxx xxxx RXB1D11 RXB1D10 xxxx xxxx RXB1D01 RXB1D00 xxxx xxxx DLC1 EID1 EID9 EID17 SID4 FILHIT1 ICODE0 TXB0D71 TXB0D61 TXB0D51 TXB0D41 TXB0D31 TXB0D21 TXB0D11 TXB0D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 ICODE0 TXB1D71 TXB1D61 TXB1D51 TXB1D41 TXB1D31 TXB1D21 TXB1D11 TXB1D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 DLC0 EID0 EID8 EID16 SID3 FILHIT0 -- -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 000- 0000 xxx- xxx- CANSTATRO2 OPMODE2 OPMODE1 OPMODE0 TXB0D70 xxxx xxxx TXB0D60 xxxx xxxx TXB0D50 xxxx xxxx TXB0D40 xxxx xxxx TXB0D30 xxxx xxxx TXB0D20 xxxx xxxx TXB0D10 xxxx xxxx TXB0D00 xxxx xxxx DLC0 EID0 EID8 EID16 SID3 TXPRI0 -- -x-- xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx -000 0-00 xxx- xxx- CANSTATRO3 OPMODE2 OPMODE1 OPMODE0 TXB1D70 xxxx xxxx TXB1D60 xxxx xxxx TXB1D50 xxxx xxxx TXB1D40 xxxx xxxx TXB1D30 xxxx xxxx TXB1D20 xxxx xxxx TXB1D10 xxxx xxxx TXB1D00 xxxx xxxx DLC0 EID0 EID8 EID16 SID3 TXPRI0 -x-- xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as '0's. 2: Bit21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read `0' in all other Oscillator modes. DS41159B-page 52 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 4-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 -- TXB2D74 TXB2D64 TXB2D54 TXB2D44 TXB2D34 TXB2D24 TXB2D14 TXB2D04 -- EID4 EID12 -- SID7 TXERR EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 EID4 EID12 -- SID7 Bit 3 ICODE2 TXB2D73 TXB2D63 TXB2D53 TXB2D43 TXB2D33 TXB2D23 TXB2D13 TXB2D03 DLC3 EID3 EID11 EXIDE SID6 TXREQ EID3 EID11 -- SID6 EID3 EID11 -- SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 Bit 2 ICODE1 TXB2D72 TXB2D62 TXB2D52 TXB2D42 TXB2D32 TXB2D22 TXB2D12 TXB2D02 DLC2 EID2 EID10 -- SID5 -- EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 EID2 EID10 -- SID5 Bit 1 ICODE0 TXB2D71 TXB2D61 TXB2D51 TXB2D41 TXB2D31 TXB2D21 TXB2D11 TXB2D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 Bit 0 -- Value on Details on POR, BOR Page: xxx- xxx33, 200 35, 206 35, 206 35, 206 35, 206 35, 206 35, 206 35, 206 35, 206 35, 207 35, 206 35, 205 35, 205 35, 205 35, 204 36, 214 36, 214 36, 214 36, 213 36, 214 36, 214 36, 214 36, 213 36, 213 36, 213 36, 212 36, 212 36, 213 36, 213 36, 212 36, 212 36, 213 36, 213 36, 212 36, 212 36, 213 36, 213 36, 212 36, 212 36, 213 36, 213 36, 212 36, 212 36, 213 36, 213 36, 212 36, 212 CANSTATRO4 OPMODE2 OPMODE1 OPMODE0 TXB2D7 TXB2D6 TXB2D5 TXB2D4 TXB2D3 TXB2D2 TXB2D1 TXB2D0 TXB2DLC TXB2EIDL TXB2EIDH TXB2SIDL TXB2SIDH TXB2CON RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EIDL RXF5EIDH RXF5SIDL RXF5SIDH RXF4EIDL RXF4EIDH RXF4SIDL RXF4SIDH RXF3EIDL RXF3EIDH RXF3SIDL RXF3SIDH RXF2EIDL RXF2EIDH RXF2SIDL RXF2SIDH RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDL RXF0EIDH RXF0SIDL RXF0SIDH TXB2D77 TXB2D67 TXB2D57 TXB2D47 TXB2D37 TXB2D27 TXB2D17 TXB2D07 -- EID7 EID15 SID2 SID10 -- EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 TXB2D76 TXB2D66 TXB2D56 TXB2D46 TXB2D36 TXB2D26 TXB2D16 TXB2D06 TXRTR EID6 EID14 SID1 SID9 TXABT EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 TXB2D75 TXB2D65 TXB2D55 TXB2D45 TXB2D35 TXB2D25 TXB2D15 TXB2D05 -- EID5 EID13 SID0 SID8 TXLARB EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 TXB2D70 xxxx xxxx TXB2D60 xxxx xxxx TXB2D50 xxxx xxxx TXB2D40 xxxx xxxx TXB2D30 xxxx xxxx TXB2D20 xxxx xxxx TXB2D10 xxxx xxxx TXB2D00 xxxx xxxx DLC0 EID0 EID8 EID16 SID3 TXPRI0 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 -x-- xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx -000 0-00 xxxx xxxx xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as '0's. 2: Bit21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read `0' in all other Oscillator modes. 2002 Microchip Technology Inc. Preliminary DS41159B-page 53 PIC18FXX8 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement that is very useful for C compiler code optimization. The techniques used by the C compiler are also useful for programs written in assembly. This data memory region can be used for: * * * * * Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read '0's, and writes will have no effect. A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 4.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM space. The Access Bank is comprised of the upper 160 bytes in Bank 15 (SFRs) and the lower 96 bytes in Bank 0. These two sections will be referred to as Access Bank High and Access Bank Low, respectively. Figure 4-6 indicates the Access Bank areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register, or in the Access Bank. When forced in the Access Bank (a = '0'), the last address in Access Bank Low is followed by the first address in Access Bank High. Access Bank High maps most of the Special Function Registers so that these registers can be accessed without any software overhead. FIGURE 4-7: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 From Opcode(3) 0 Bank Select(2) Location Select(3) 00h 000h 01h 100h 0Eh E00h 0Fh F00h Data Memory(1) 0FFh 1FFh EFFh FFFh Bank 0 Note 1: For register file map detail, see Table 4-1. Bank 1 Bank 14 Bank 15 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS41159B-page 54 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. A SFR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-8 shows the operation of indirect addressing. This shows the moving of the value to the data memory address specified by the value of the FSR register. Indirect addressing is possible by using one of the INDF registers. Any instruction using the INDF register actually accesses the register indicated by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = '0'), will read 00h. Writing to the INDF register indirectly, results in a no operation. The FSR register contains a 12-bit address, which is shown in Figure 4-8. The INDFn (0 n 2) register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 4-5 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions. If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all '0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the STATUS bits are not affected. 4.12.1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect addressing. * When data access is done to one of the five INDFn locations, the address selected will configure the FSRn register to: - Do nothing to FSRn after an indirect access (no change) - INDFn - Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn - Auto-increment FSRn after an indirect access (post-increment) - POSTINCn - Auto-increment FSRn before an indirect access (pre-increment) - PREINCn - Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect address causes the FSR to equal '0', the Z bit will not be set. Incrementing or decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a software stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the 2's complement value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. If an FSR register contains a value that indicates one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (STATUS bits are not affected). If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or postincrement/decrement functions. EXAMPLE 4-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; ; ; ; ; ; ; ; Clear INDF register & inc pointer All done w/ Bank1? NO, clear next YES, continue LFSR NEXT CLRF BTFSS BRA CONTINUE : FSR0H, 1 NEXT There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bits wide. To store the 12 bits of addressing information, two 8-bit registers are required. These indirect addressing registers are: 1. FSR0: composed of FSR0H:FSR0L 2. FSR1: composed of FSR1H:FSR1L 3. FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address indicated by FSR0H:FSR0L. A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2002 Microchip Technology Inc. Preliminary DS41159B-page 55 PIC18FXX8 FIGURE 4-8: INDIRECT ADDRESSING Indirect Addressing FSR Register 11 8 FSRnH Location Select 7 FSRnL 0 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-1. DS41159B-page 56 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 4.13 STATUS Register The STATUS register, shown in Register 4-2, contains the arithmetic status of the ALU. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV, or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV, or N bits from the STATUS register. For other instructions which do not affect the status bits, see Table 25-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-2: STATUS REGISTER U-0 -- bit 7 U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC R/W-x C bit 0 bit 7-5 bit 4 Unimplemented: Read as '0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result of the ALU operation was negative (ALU MSb = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and RLNCF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 3 bit 2 bit 1 bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 57 PIC18FXX8 4.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. Note 1: If the BOREN configuration bit is set, BOR is '1' on Power-on Reset. If the BOREN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brownout circuit is disabled (the BOREN configuration bit is clear). BOR must then be set by the user and checked on subsequent RESETS to see if it is clear, indicating a brown-out has occurred. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 4-3: RCON REGISTER R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX Compatibility mode) Unimplemented: Read as '0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device RESET (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 58 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 5.0 DATA EEPROM MEMORY 5.1 EEADR Register The Data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR The address register can address up to a maximum of 256 bytes of data EEPROM. 5.2 EECON1 and EECON2 Registers EECON1 is the control register for EEPROM memory accesses. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the EEPROM write sequence. Control bits RD and WR initiate read and write operations, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset, during normal operation. In these situations, following RESET, the user can check the WRERR bit and rewrite the location. The data and address registers (EEDATA and EEADR) remain unchanged. The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. The PIC18FXX8 devices have 256 bytes of data EEPROM, with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/ write cycles. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to the specifications for exact limits. Note: Interrupt flag bit EEIF in the PIR2 register is set when write is complete. It must be cleared in software. 2002 Microchip Technology Inc. Preliminary DS41159B-page 59 PIC18FXX8 REGISTER 5-1: EECON1 REGISTER R/W-x EEPGD bit 7 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access program FLASH memory 0 = Access data EEPROM memory CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program FLASH or data EEPROM memory Unimplemented: Read as '0' FREE: FLASH Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (reset by hardware) 0 = Perform write only WRERR: Write Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: bit 2 When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 bit 6 bit 5 bit 4 bit 3 WREN: Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM or FLASH memory WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 1 bit 0 DS41159B-page 60 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 5.3 Reading the Data EEPROM Memory 5.4 Writing to the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD and CFGS control bits (EECON1<7:6>) and then set control bit RD (EECON1<0>). The data is available in the very next instruction cycle of the EEDATA register; therefore, it can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. Then, the sequence in Example 5-2 must be followed to initiate the write cycle. The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Write Complete Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt, or roll this bit. EEIF must be cleared by software. EXAMPLE 5-1: MOVLW MOVWF BCF BCS BSF MOVF DATA EEPROM READ ; ;Data Memory Address ;to read ;Point to DATA memory ; ;EEPROM Read ;W = EEDATA DATA_EE_ADDR EEADR EECON1, EECON1, EECON1, EEDATA, EEPGD CFGS RD W EXAMPLE 5-2: DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF BCF BCS BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; ; Data Memory Address to write Data Memory Value to write Point to DATA memory Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Enable Interrupts Required Sequence BCF EECON1, WREN ; User code execution ; Disable writes 2002 Microchip Technology Inc. Preliminary DS41159B-page 61 PIC18FXX8 5.5 Write Verify 5.7 Operation During Code Protect Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Generally, a write failure will be a bit which was written as a '1', but reads back as a '0' (due to leakage off the cell). Data EEPROM memory has its own code protect mechanism. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code protect configuration bit. Refer to Section 24.0, Special Features of the CPU for additional information. 5.8 5.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together reduce the probability of an accidental write during brown-out, power glitch, or software malfunction. Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124 or D124A. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in FLASH program memory. A simple data EEPROM refresh routine is shown in Example 5-3. Note: If Data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124 or D124A. EXAMPLE 5-3: clrf bcf bcf bcf bsf Loop bsf movlw movwf movlw movwf bsf btfsc bra incfsz bra bcf bsf DATA EEPROM REFRESH ROUTINE EEADR EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,WREN EECON1,RD 55h EECON2 AAh EECON2 EECON1,WR EECON1,WR $-2 EEADR,F Loop EECON1,WREN INTCON,GIE ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete ; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts DS41159B-page 62 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 5-1: Name INTCON EEADR EEDATA EECON2 EECON1 IPR2 PIR2 PIE2 Legend: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 INT0IE Bit 3 RBIE Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF Value on: POR, BOR Value on all other RESETS GIE/GIEH PEIE/GIEL TMR0IE EEPROM Address Register EEPROM Data Register 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- -- EEPROM Control Register2 (not a physical register) EEPGD -- -- -- CFGS CMIP CMIF CMIE -- -- -- -- FREE EEIP EEIF EEIE WRERR BCLIP BCLIF BCLIE WREN LVDIP LVDIF LVDIE WR TMR3IP TMR3IF TMR3IE RD xx-0 x000 uu-0 u000 ECCP1IP -1-1 1111 -1-1 1111 ECCP1IF -0-0 0000 -0-0 0000 ECCP1IE -0-0 0000 -0-0 0000 x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. 2002 Microchip Technology Inc. Preliminary DS41159B-page 63 PIC18FXX8 NOTES: DS41159B-page 64 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The FLASH Program Memory is readable, writable, and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16-bits wide, while the data RAM space is 8-bits wide. Table Reads and Table Writes move data between these two memory spaces through an 8-bit register (TABLAT). Table Read operations retrieve data from program memory and places it into the data RAM space. Figure 6-1 shows the operation of a Table Read with program memory and data RAM. Table Write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5, Writing to FLASH Program Memory. Figure 6-2 shows the operation of a Table Write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a Table Write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Program Memory Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2002 Microchip Technology Inc. Preliminary DS41159B-page 65 PIC18FXX8 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 6.5. 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), due to RESET values of zero. Control bits RD and WR initiate read and write operations, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). 6.2.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit EEPGD determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. Control bit CFGS determines if the access will be to the configuration/calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on configuration registers, regardless of EEPGD (see Section 24.0, Special Features of the CPU). When clear, memory selection access is determined by EEPGD. Note: If interrupts are enabled before the WR command, interrupt flag bit EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. This interrupt is not required to determine the end of a FLASH program memory write cycle. DS41159B-page 66 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 6-1: EECON1 REGISTER R/W-x EEPGD bit 7 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access program FLASH memory 0 = Access data EEPROM memory CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program FLASH or data EEPROM memory Unimplemented: Read as '0' FREE: FLASH Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: Write Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: bit 2 When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 bit 6 bit 5 bit 4 bit 3 WREN: Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM or FLASH memory WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 1 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 67 PIC18FXX8 6.2.2 TABLAT - TABLE LATCH REGISTER 6.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes, and erases of the FLASH program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer, TBLPTR (TBLPTR<21:3>), will determine which program memory block of 8 bytes is written to. For more detail, see Section 6.5,Writing to FLASH Program Memory. When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on FLASH program memory operations. 6.2.3 TBLPTR - TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID, the User ID and the Configuration bits. The table pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways, based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low order 21 bits. TABLE 6-1: Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write FIGURE 6-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE - TBLPTR<21:6> WRITE - TBLPTR<21:3> READ - TBLPTR<21:0> DS41159B-page 68 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 6.3 Reading the FLASH Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and place into data RAM. Table Reads from program memory are performed one byte at a time. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register (IR) FETCH TBLRD TABLAT Read Register EXAMPLE 6-1: MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD READING A FLASH PROGRAM MEMORY WORD CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word TBLRD*+ MOVF TABLAT, W MOVWF WORD_LSB TBLRD*+ MOVF TABLAT, W MOVWF WORD_MSB ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data 2002 Microchip Technology Inc. Preliminary DS41159B-page 69 PIC18FXX8 6.4 Erasing FLASH Program memory 6.4.1 The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the FLASH array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the FLASH program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. 2. Load table pointer with address of row being erased. Set the EECON1 register for the erase operation: * set the EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set the WREN bit to enable writes; * set the FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. Note: A NOP is needed after the WR command to ensure proper code execution. 3. 4. 5. 6. 7. 8. 9. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF upper (CODE_ADDR) TBLPTRU high (CODE_ADDR) TBLPTRH low (CODE_ADDR) TBLPTRL EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 0AAh EECON2 EECON1,WR INTCON,GIE ; load TBLPTR with the base ; address of the memory block ERASE_ROW BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF ; ; ; ; ; point to FLASH program memory access FLASH program memory enable write to memory enable Row Erase operation disable interrupts ; write 55H ; ; ; ; write 0AAH start erase (CPU stall) NOP needed for proper code execution re-enable interrupts Required Sequence DS41159B-page 70 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 6.5 Writing to FLASH Program Memory 5. 6. Load Table Pointer with address of first byte being written. Write the first 8 bytes into the holding registers using the TBLWT instruction, auto-increment may be used. Set the EECON1 register for the write operation: * set the EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set the WREN to enable byte writes. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. Repeat steps 6-14 seven times, to write 64 bytes. Verify the memory (Table Read). The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table Writes are used internally to load the holding registers needed to program the FLASH memory. There are 8 holding registers used by the Table Writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the Table Write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Note 1: A NOP is needed after the WR command to ensure proper code execution. 2: Before setting the WR bit, the Table Pointer address needs to be within the range of addresses of the 8 bytes in the holding registers. 3: Holding registers are cleared on RESET and at the completion of each write cycle. 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 8 TBLPTR = xxxxx2 8 TBLPTR = xxxxx7 8 Holding Register Holding Register Holding Register Holding Register Program Memory 2002 Microchip Technology Inc. Preliminary DS41159B-page 71 PIC18FXX8 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVF MOVWF DECFSZ BRA MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF NOP BSF TBLRD*WRITE_BUFFER_BACK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PROGRAM_LOOP MOVLW MOVWF WRITE_WORD_TO_HREGS MOVFW MOVWF TBLWT+* upper (CODE_ADDR) TBLPTRU high (CODE_ADDR) TBLPTRH low (CODE_ADDR) TBLPTRL EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT, W POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat D'64 COUNTER high (BUFFER_ADDR) FSR0H low (BUFFER_ADDR) FSR0L upper (CODE_ADDR) TBLPTRU high (CODE_ADDR) TBLPTRH low (CODE_ADDR) TBLPTRL ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; update buffer word ; ; ; ; ; point to FLASH program memory access FLASH program memory enable write to memory enable Row Erase operation disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts ; dummy read decrement ; number of write buffer groups of 8 bytes ; point to buffer 8 COUNTER_HI high (BUFFER_ADDR) FSR0H low (BUFFER_ADDR) FSR0L 8 COUNTER POSTINC0, W TABLAT ; number of bytes in holding register DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full DS41159B-page 72 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full WRITE_WORD_TO_HREGS MOVFW POSTINC0, W MOVWF TABLAT TBLWT+* DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF DECFSZ BRA BCF EECON1,EEPGD EECON1,CFGS EECON1,WREN INTCON,GIE 55h EECON2 0AAh EECON2 EECON1,WR INTCON,GIE COUNTER_HI PROGRAM_LOOP EECON1,WREN ; ; ; ; ; point to FLASH program memory access FLASH program memory enable write to memory disable interrupts write 55H Required Sequence ; write 0AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ; disable write to memory 6.5.2 WRITE VERIFY 6.5.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. PROTECTION AGAINST SPURIOUS WRITES To reduce the probability against spurious writes to FLASH program memory, the write initiate sequence must also be followed. See Section 24.0, Special Features of the CPU for more detail. 6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION 6.6 FLASH Program Operation During Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected RESET, the memory location just programmed should be verified and reprogrammed if needed.The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. See Section 24.0, Special Features of the CPU for details on code protection of FLASH program memory. 2002 Microchip Technology Inc. Preliminary DS41159B-page 73 PIC18FXX8 TABLE 6-2: Name TBLPTRU Bit 7 -- REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 6 -- Bit 5 bit21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR --00 0000 0000 0000 0000 0000 0000 0000 Value on all other RESETS --00 0000 0000 0000 0000 0000 0000 0000 0000 000u Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Legend: Program Memory Table Latch GIE/GIEH PEIE/GIEL TMR0IE EEPGD -- -- -- CFGS -- -- -- -- -- -- -- INTE FREE EEIP EEIF EEIE RBIE WRERR BCLIP BCLIF BCLIE TMR0IF WREN LVDIP LVDIF LVDIE INTF WR TMR3IP TMR3IF TMR3IE RBIF RD CCP2IP CCP2IF CCP2IE EEPROM Control Register2 (not a physical register) 0000 000x -- xx-0 x000 ---1 1111 ---0 0000 ---0 0000 -- uu-0 u000 ---1 1111 ---0 0000 ---0 0000 x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access. DS41159B-page 74 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 7.0 7.1 8 X 8 HARDWARE MULTIPLIER Introduction 7.2 Operation An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX8 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the ALUSTA register. Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Table 7-1 shows a performance comparison between enhanced devices using the single cycle hardware multiply, and performing the same function without the hardware multiply. Example 7-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 7-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. EXAMPLE 7-1: MOVF MULWF ARG1, W ARG2 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 7-2: MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, ARG2 ARG2, PRODH ARG2, ARG1, PRODH W 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 SB W SB ; Test Sign Bit ; PRODH = PRODH ; - ARG2 TABLE 7-1: Routine PERFORMANCE COMPARISON Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 24 52 36 Cycles (Max) 69 1 91 6 242 24 254 36 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.4 s 25.4 s 3.6 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 9.6 s 102.6 s 14.4 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 24 s 254 s 36 s 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed 2002 Microchip Technology Inc. DS41159B-page 75 PIC18FXX8 Example 7-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 7-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM EQUATION 7-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216)+ (ARG1H * ARG2L * 28)+ (ARG1L * ARG2H * 28)+ (ARG1L * ARG2L) RES3:RES0 = = RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216)+ (ARG1H * ARG2L * 28)+ (ARG1L * ARG2H * 28)+ (ARG1L * ARG2L)+ (-1 * ARG2H<7> * ARG1H:ARG1L * 216)+ (-1 * ARG1H<7> * ARG2H:ARG2L * 216) EXAMPLE 7-4: MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : 16 x 16 SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; EXAMPLE 7-3: MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC 16 x 16 UNSIGNED MULTIPLY ROUTINE ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1 PRODH, W RES2 WREG RES3 ARG1H, W ARG2L PRODL, W RES1 PRODH, W RES2 WREG RES3 ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ARG1L, W ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; ARG1H, W ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; ARG1L, W ARG2H PRODL, W RES1 PRODH, W RES2 WREG RES3 ARG1H, W ARG2L PRODL, W RES1 PRODH, W RES2 WREG RES3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; Example 7-4 shows the sequence to do a 16 x 16 signed multiply. Equation 7-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs Most Significant bit (MSb) is tested and the appropriate subtractions are done. ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; DS41159B-page 76 2002 Microchip Technology Inc. PIC18FXX8 8.0 INTERRUPTS The PIC18FXX8 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h, and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are 13 registers that are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. The PEIE bit (INTCON register) enables/disables all peripheral interrupt sources. The GIE bit (INTCON register) enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts, to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit, or the GIE bit. It is recommended that the Microchip header files supplied with MPLAB(R) IDE, be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON register). When interrupt priority is enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts. Setting the GIEL bit (INTCON register) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. 2002 Microchip Technology Inc Preliminary DS41159B-page 77 PIC18FXX8 FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Wake-up if in SLEEP mode Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN IPEN GIEL/PEIE IPEN Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP Interrupt to CPU Vector to Location 0018h TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP PEIE/GIEL GIE/GIEH DS41159B-page 78 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 8.1 INTCON Registers Note: The INTCON Registers are readable and writable registers, which contain various enable, priority, and flag bits. Because of the number of interrupts to be controlled, PIC18FXX8 devices have three INTCON registers. They are detailed in Register 8-1 through Register 8-3. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. REGISTER 8-1: INTCON REGISTER R/W-0 bit 7 R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF bit 0 GIE/GIEH PEIE/GIEL bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN (RCON<7>) = 1: 1 = Enables all high priority interrupts 0 = Disables all priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN (RCON<7>) = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software by reading PORTB) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1 bit 0 2002 Microchip Technology Inc Preliminary DS41159B-page 79 PIC18FXX8 REGISTER 8-2: INTCON2 REGISTER R/W-1 RBPU bit 7 bit 7 R/W-1 R/W-1 U-0 -- U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP bit 0 INTEDG0 INTEDG1 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplmented: Read as '0' TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplmented: Read as '0' RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4-3 bit 2 bit 1 bit 0 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. DS41159B-page 80 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 8-3: INTCON3 REGISTER R/W-1 INT2IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplmented: Read as '0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplmented: Read as '0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 INT1IP U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2002 Microchip Technology Inc Preliminary DS41159B-page 81 PIC18FXX8 8.2 PIR Registers The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts (Register 8-4 through Register 8-6). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON register). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. REGISTER 8-4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (PIR1) R/W-0 PSPIF(1) bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 =The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 =The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as '0'. bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 82 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 8-5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2) U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' CMIF: Comparator Interrupt Flag bit (1) 1 = Comparator input has changed 0 = Comparator input has not changed Unimplemented: Read as'0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = Write operation is complete (must be cleared in software) 0 = Write operation is not complete BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low Voltage Detect trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow ECCP1IF: ECCP1 Interrupt Flag bit (1) Capture mode: 1 = A TMR1 (TMR3) register capture occurred (must be cleared in software) 0 = No TMR1 (TMR3) register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as '0'. R/W-0 CMIF(1) U-0 -- R/W-0 EEIF R/W-0 BCLIF R/W-0 LVDIF R/W-0 TMR3IF R/W-0 ECCP1IF(1) bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc Preliminary DS41159B-page 83 PIC18FXX8 REGISTER 8-6: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (PIR3) R/W-0 IRXIF bit 7 bit 7 IRXIF: Invalid Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = An invalid message has not occurred on the CAN bus WAKIF: Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = Activity on the CAN bus has not occurred ERRIF: CAN Bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = An error has not occurred in the CAN module TXB2IF: Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message TXB1IF: Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message RXB1IF: Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXB2IF R/W-0 TXB1IF R/W-0 TXB0IF R/W-0 RXB1IF R/W-0 RXB0IF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 84 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 8.3 PIE Registers The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts (Register 8-7 through Register 8-9). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN is clear, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 8-7: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1) R/W-0 PSPIE bit 7 (1) R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as '0'. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc Preliminary DS41159B-page 85 PIC18FXX8 REGISTER 8-8: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2) U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' CMIE: Comparator Interrupt Enable bit(1) 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt Unimplemented: Read as '0' EEIE: EEPROM Write Interrupt Enable bit 1 = Enabled 0 = Disabled BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt ECCP1IE: ECCP1 Interrupt Enable bit (1) 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as '0'. R/W-0 CMIE(1) U-0 -- R/W-0 EEIE R/W-0 BCLIE R/W-0 LVDIE R/W-0 TMR3IE R/W-0 ECCP1IE(1) bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 86 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 8-9: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (PIE3) R/W-1 IRXIE bit 7 bit 7 IRXIE: Invalid CAN Message Received Interrupt Enable bit 1 = Enables the invalid CAN message received interrupt 0 = Disables the invalid CAN message received interrupt WAKIE: Bus Activity Wake-up Interrupt Enable bit 1 = Enables the bus activity wake-up interrupt 0 = Disables the bus activity wake-up interrupt ERRIE: CAN bus Error Interrupt Enable bit 1 = Enables the CAN bus error interrupt 0 = Disables the CAN bus error interrupt TXB2IE: Transmit Buffer 2 Interrupt Enable bit 1 = Enables the Transmit Buffer 2 interrupt 0 = Disables the Transmit Buffer 2 interrupt TXB1IE: Transmit Buffer 1 Interrupt Enable bit 1 = Enables the Transmit Buffer 1 interrupt 0 = Disables the Transmit Buffer 1 interrupt TXB0IE: Transmit Buffer 0 Interrupt Enable bit 1 = Enables the Transmit Buffer 0 interrupt 0 = Disables the Transmit Buffer 0 interrupt RXB1IE: Receive Buffer 1 Interrupt Enable bit 1 = Enables the Receive Buffer 1 interrupt 0 = Disables the Receive Buffer 1 interrupt RXB0IE: Receive Buffer 0 Interrupt Enable bit 1 = Enables the Receive Buffer 0 interrupt 0 = Disables the Receive Buffer 0 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 WAKIE R/W-1 ERRIE R/W-1 TXB2IE R/W-1 TXB1IE R/W-1 TXB0IE R/W-1 RXB1IE R/W-1 RXB0IE bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2002 Microchip Technology Inc Preliminary DS41159B-page 87 PIC18FXX8 8.4 IPR Registers The Interrupt Priority (IPR) registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable bit (IPEN) be set. REGISTER 8-10: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (IPR1) R/W-1 PSPIP(1) bit 7 R/W-1 ADIP R/W-1 RCIP R/W-1 TXIP R/W-1 SSPIP R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority CCP1IP: CCP1 Interrupt Priority bit 1 =High priority 0 =Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as '0'. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 88 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 8-11: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2) U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' CMIP: Comparator Interrupt Priority bit(1) 1 = High priority 0 = Low priority Unimplemented: Read as '0' EEIP: EEPROM Write Interrupt Priority bit 1 = High priority 0 = Low priority BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority ECCP1IP: ECCP1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as '0'. R/W-1 CMIP(1) U-0 -- R/W-0 EEIP R/W-1 BCLIP R/W-1 LVDIP R/W-1 TMR3IP R/W-1 ECCP1IP(1) bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc Preliminary DS41159B-page 89 PIC18FXX8 REGISTER 8-12: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (IPR3) R/W-1 IRXIP bit 7 bit 7 IRXIP: Invalid Message Received Interrupt Priority bit 1 = High priority 0 = Low priority WAKIP: Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority RXB1IP: Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority RXB0IP: Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 WAKIP R/W-1 ERRIP R/W-1 TXB2IP R/W-1 TXB1IP R/W-1 TXB0IP R/W-1 RXB1IP R/W-1 RXB0IP bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 90 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 8.5 RCON Register The Reset Control (RCON) register contains the IPEN bit, which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14. REGISTER 8-13: RCON REGISTER R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX Compatibility mode) Unimplemented: Read as '0' RI: RESET Instruction Flag bit For details of bit operation, see Register 4-3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-3 PD: Power-down Detection Flag bit For details of bit operation, see Register 4-3 POR: Power-on Reset Status bit For details of bit operation, see Register 4-3 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-3 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 2002 Microchip Technology Inc Preliminary DS41159B-page 91 PIC18FXX8 8.6 INT Interrupts 8.8 PORTB Interrupt-on-Change External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxIF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxIE. Flag bit INTxIF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from SLEEP, if bit INTxIE was set prior to going into SLEEP. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0; it is always a high priority interrupt source. An input change on PORTB<7:4> sets flag bit RBIF (INTCON register). The interrupt can be enabled/ disabled by setting/clearing enable bit RBIE (INTCON register). Interrupt priority for PORTB interrupt-onchange is determined by the value contained in the interrupt priority bit RBIP (INTCON2 register). 8.9 Context Saving During Interrupts During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 4.3), the user may need to save the WREG, STATUS and BSR registers in software. Depending on the user's application, other registers may also need to be saved. Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16bit mode, an overflow (FFFFh 0000h) in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON register). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2 register). See Section 11.0 for further details on the Timer0 module. EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM ; W_TEMP is in Low Access bank ; STATUS_TEMP located anywhere ; BSR located anywhere MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS ; Restore BSR ; Restore WREG ; Restore STATUS DS41159B-page 92 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 9.0 I/O PORTS FIGURE 9-1: Depending on the device selected, there are up to five general purpose I/O ports available on PIC18FXX8 devices. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch). The data latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. WR TRISA Analog Input Mode RA3:RA0 AND RA5 PINS BLOCK DIAGRAM RD LATA Data Bus WR LATA or WR PORTA D CK Q VDD Q P Data Latch D CK Q N I/O pin(1) Q VSS TRIS Latch 9.1 PORTA, TRISA and LATA Registers RD TRISA Q D EN RD PORTA SS Input (RA5 only) To A/D Converter and LVD Modules TTL Input Buffer PORTA is a 7-bit wide, bi-directional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= `1') will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= `0') will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). On a Power-on Reset, these pins are configured as inputs and read as '0'. Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. Read-modify-write operations on the LATA register, reads and writes the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set, when using them as analog inputs. Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 9-2: RA4/T0CKI PIN BLOCK DIAGRAM RD LATA Data Bus WR LATA or WR PORTA D Q CK Q N I/O pin(1) Data Latch D WR TRISA CK Q Q TTL Input Buffer VSS Schmitt Trigger Input Buffer TRIS Latch RD TRISA EXAMPLE 9-1: CLRF CLRF MOVLW MOVWF MOVLW PORTA ; ; LATA ; ; 07h ; ADCON1 ; 0xCF ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA3:RA0 as inputs, RA5:RA4 as outputs Q D EN RD PORTA TMR0 Clock Input Note 1: I/O pin has diode protection to VSS only. MOVWF 2002 Microchip Technology Inc. Preliminary DS41159B-page 93 PIC18FXX8 FIGURE 9-3: RA6/OSC2/CLKOUT PIN BLOCK DIAGRAM (FOSC = 101, 111) CLKO (FOSC/4) 1 Data Latch Data Bus D CK Q 0 VDD P RA6/OSC2/ CLKO pin(2) From OSC1 Oscillator Circuit WR PORTA Q TRIS Latch D WR TRISA (FOSC = 100, 101, 110, 111) CK Q N Q VSS Schmitt Trigger Input Buffer RD TRISA Q D Data Latch EN RD PORTA (FOSC = 110, 100) Note 1: CLKO is 1/4 of FOSC. 2: I/O pin has diode protection to VDD and VSS. TABLE 9-1: Name RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI PORTA FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer TTL TTL TTL TTL TTL TTL Function Input/output, analog input, or analog comparator voltage reference output. Input/output or analog input. Input/output, analog input or VREF-. Input/output, analog input or VREF+. Input/output, slave select input for synchronous serial port, analog input, or low voltage detect input. Input/output or oscillator clock output. ST/OD Input/output, external clock input for Timer0, output is open drain type. RA5/SS/AN4/LVDIN RA6/OSC2/CLKO Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain TABLE 9-2: Name PORTA LATA TRISA ADCON1 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 -- -- -- Bit 6 RA6 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR Value on all other RESETS -00x 0000 -uuu uuuu -xxx xxxx -uuu uuuu -111 1111 -111 1111 Latch A Data Output Register PORTA Data Direction Register -- -- PCFG3 PCFG2 PCFG1 ADFM ADCS2 PCFG0 00-- 0000 uu-- uuuu Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS41159B-page 94 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= `1') will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= `0') will make the corresponding PORTB pin an output ( i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATB register, read and write the latched output value for PORTB. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2 register). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON register). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit RBIF. EXAMPLE 9-2: CLRF PORTB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB3:RB0 as inputs RB5:RB4 as outputs RB7:RB6 as inputs CLRF LATB MOVLW 0CFh MOVWF TRISB b) FIGURE 9-4: RB7:RB4 PINS BLOCK DIAGRAM VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q CK TTL Input Buffer Q I/O pin(1) A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RBPU(2) Data Bus WR LATB or WR PORTB FIGURE 9-5: RB1:RB0 PINS BLOCK DIAGRAM VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q Q I/O pin(1) RBPU(2) WR TRISB ST Buffer Data Bus WR Port RD TRISB RD LATB Latch Q RD PORTB EN Set RBIF Q1 RD TRIS D WR TRIS CK TTL Input Buffer Q From other RB7:RB4 pins RBx/INTx D EN Q3 RD Port RBx/INTx Q D EN Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). Schmitt Trigger Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). 2002 Microchip Technology Inc. Preliminary DS41159B-page 95 PIC18FXX8 FIGURE 9-6: RB2/CANTX BLOCK DIAGRAM OPMODE2:OPMODE0 = 000 ENDRHI CANTX 0 VDD Data Latch D Q CK Q RB2 pin(1) N WR TRISB CK Q VSS Schmitt Trigger Q D EN RD LATB Data Bus WR PORTB or WR LATB 1 P TRIS Latch D Q RD TRISB RD PORTB Note 1: I/O pin has diode protection to VDD and VSS. FIGURE 9-7: BLOCK DIAGRAM OF RB3/CANRX PIN CANCON<7:5> RBPU(2) Data Latch Data Bus WR LATB or PORTB D CK TRIS Latch D Q WR TRISB CK TTL Input Buffer Q I/O pin(1) VDD P Weak Pull-up RD TRISB RD LATB Q D EN RD PORTB RB3 or CANRX Schmitt Trigger Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). . DS41159B-page 96 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 9-3: Name RB0/INT0 RB1/INT1 RB2/INT2/ CANTX RB3/CANRX RB4 RB5/PGM RB6/PGC RB7/PGD PORTB FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Function TTL/ST(1) Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. TTL/ST(1) Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. TTL/ST(1) Input/output pin, external interrupt 2 input or CAN bus transmit pin. Internal software programmable weak pull-up. TTL TTL TTL Input/output pin or CAN bus receive pin. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low voltage serial programming enable. TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 9-4: Name PORTB LATB TRISB INTCON INTCON2 INTCON3 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 INT0IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 000u 1111 -1-1 11-0 0-00 LATB Data Output Register PORTB Data Direction Register GIE/GIEH PEIE/GIEL RBPU INT2IP TMR0IE INTEDG0 INTEDG1 INTEDG2 INT1IP -- INT2IE Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. 2002 Microchip Technology Inc. Preliminary DS41159B-page 97 PIC18FXX8 9.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= `1') will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= `0') will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATC register, read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 9-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. EXAMPLE 9-3: CLRF PORTC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC3:RC0 as inputs RC5:RC4 as outputs RC7:RC6 as inputs CLRF LATC MOVLW 0CFh MOVWF TRISC FIGURE 9-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) Peripheral Out Select Peripheral Data Out 0 RD LATC Data Bus WR LATC or WR PORTC D CK Q Q VDD P 1 I/O pin(1) N Pin TRIS Override VSS RC0 RC1 Schmitt Trigger Q D Data Latch D Q Q TRIS OVERRIDE Override Yes Yes No Yes Yes Yes Yes Yes Peripheral Timer1 OSC for Timer1/Timer3 Timer1 OSC for Timer1/Timer3 -- SPI/I2C Master Clock I2C Data Out SPI Data Out USART Async Xmit, Sync Clock USART Sync Data Out WR TRISC CK TRIS Latch RD TRISC Peripheral Enable RC2 RC3 RC4 EN RD PORTC Peripheral Data In RC5 RC6 RC7 Note 1: I/O pins have diode protection to VDD and VSS. DS41159B-page 98 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 9-5: Name RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTC FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin or Timer1 oscillator input. Input/output port pin or Capture1 input/Compare1 output/PWM1 output. Input/output port pin or Synchronous Serial clock for SPI/I2C. Input/output port pin or SPI Data in (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin, Addressable USART Asynchronous Transmit or Addressable USART Synchronous Clock. Input/output port pin, Addressable USART Asynchronous Receive or Addressable USART Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 9-6: Name PORTC LATC TRISC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 LATC Data Output Register PORTC Data Direction Register Legend: x = unknown, u = unchanged 2002 Microchip Technology Inc. Preliminary DS41159B-page 99 PIC18FXX8 9.4 Note: PORTD, TRISD and LATD Registers This port is only available PIC18F448 and PIC18F458. on the PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port, or PSP) by setting the control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.0 for additional information on the Parallel Slave Port. PORTD is also multiplexed with the analog comparator module and the ECCP module. PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register for the port is TRISD. Setting a TRISD bit (= `1') will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= `0') will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATD register reads and writes the latched output value for PORTD. PORTD is uses Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. EXAMPLE 9-4: CLRF PORTD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches comparator off Value used to initialize data direction Set RD3:RD0 as inputs RD5:RD4 as outputs RD7:RD6 as inputs CLRF LATD MOVLW MOVWF MOVLW 07h CMCON 0CFh MOVWF TRISD FIGURE 9-9: PORTD BLOCK DIAGRAM IN I/O PORT MODE PORT/PSP Select PSP Data Out RD LATD VDD P Data Bus WR LATD or PORTD D CK Q Q N RD0 pin(1) Data Latch D Q Q Vss WR TRISD CK TRIS Latch RD TRISD PSP Read Schmitt Trigger Q D EN RD PORTD PSP Write C1IN+ Note 1: I/O pins have diode protection to VDD and VSS. DS41159B-page 100 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 9-7: Name RD0/PSP0/C1IN+ RD1/PSP1/C1INRD2/PSP2/C2IN+ RD3/PSP3/C2INRD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D PORTD FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL (1) Function Input/output port pin, parallel slave port bit0 or C1IN+ Comparator input. Input/output port pin, parallel slave port bit1 or C1IN- Comparator input. Input/output port pin, parallel slave port bit2 or C2IN+ Comparator input. Input/output port pin, parallel slave port bit3 or C2IN- Comparator input. Input/output port pin, parallel slave port bit4 or ECCP1/P1A pin. Input/output port pin, parallel slave port bit5 or ECCP1/P1B pin. Input/output port pin, parallel slave port bit6 or ECCP1/P1C pin. Input/output port pin, parallel slave port bit7 or ECCP1/P1D pin. ST/TTL(1) Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 9-8: Name PORTD LATD TRISD TRISE SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 -- TRISE2 TRISE1 TRISE0 0000 -111 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 -111 Bit 7 RD7 LATD Data Output Register PORTD Data Direction Register IBF OBF IBOV PSPMODE Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD. 2002 Microchip Technology Inc. Preliminary DS41159B-page 101 PIC18FXX8 9.5 Note: PORTE, TRISE and LATE Registers This port is only available PIC18F448 and PIC18F458. on the When the Parallel Slave Port is active, the PORTE pins function as its control inputs. For additional details, refer to Section 10.0. PORTE pins are also multiplexed with inputs for the A/D converter and outputs for the analog comparators. When selected as an analog input, these pins will read as '0's. Direction bits TRISE<2:0> control the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. PORTE is a 3-bit wide, bi-directional port. PORTE has three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and RE2/AN7/CS/C2OUT), which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. Read-modify-write operations on the LATE register, reads and writes the latched output value for PORTE. The corresponding Data Direction register for the port is TRISE. Setting a TRISE bit (= `1') will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= `0') will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). The TRISE register also controls the operation of the Parallel Slave Port, through the control bits in the upper half of the register. These are shown in Register 9-1. EXAMPLE 9-5: CLRF PORTE INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE1:RE0 as inputs RE2 as an output (RE4=0 - PSPMODE Off) CLRF LATE MOVLW 03h MOVWF TRISE FIGURE 9-10: PORTE BLOCK DIAGRAM Peripheral Out Select Peripheral Data Out 0 RD LATE Data Bus WR LATE or WR PORTE D CK Q Q N TRIS Override VSS I/O pin(1) 1 VDD P Data Latch D WR TRISE CK Q Q TRIS Latch RD TRISE Peripheral Enable Q D EN RD PORTE Peripheral Data In Note 1: I/O pins have diode protection to VDD and VSS. Schmitt Trigger Pin RE0 RE1 RE2 TRIS OVERRIDE Override Peripheral Yes Yes Yes PSP PSP PSP DS41159B-page 102 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 9-1: TRISE REGISTER R-0 IBF bit 7 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode Unimplemented: Read as '0' TRISE2: RE2 Direction Control bit 1 = Input 0 = Output TRISE1: RE1 Direction Control bit 1 = Input 0 = Output TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TABLE 9-9: Name RE0/AN5/RD PORTE FUNCTIONS Bit# bit0 bit1 bit2 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) Function Input/output port pin, analog input or read control input in Parallel Slave Port mode. Input/output port pin, analog input, write control input in Parallel Slave Port mode or Comparator 1 output. Input/output port pin, analog input, chip select control input in Parallel Slave Port mode or Comparator 2 output. RE1/AN6/WR/C1OUT RE2/AN7/CS/C2OUT Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. 2002 Microchip Technology Inc. Preliminary DS41159B-page 103 PIC18FXX8 TABLE 9-10: Name TRISE PORTE LATE Bit 7 IBF -- -- SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 6 OBF -- -- Bit 5 Bit 4 Bit 3 -- -- -- Bit 2 TRISE2 Bit 1 TRISE1 Bit 0 TRISE0 Value on: POR, BOR 0000 -111 ---- -xxx ---- -xxx Value on all other RESETS 0000 -111 ---- -uuu ---- -uuu IBOV PSPMODE -- -- -- -- Read PORTE pin/ Write PORTE Data Latch Read PORTE Data Latch/ Write PORTE Data Latch Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE. DS41159B-page 104 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 10.0 Note: PARALLEL SLAVE PORT The Parallel Slave Port is only available on PIC18F4X8 devices. FIGURE 10-1: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 9-1). Setting control bit PSPMODE (TRISE<4>) enables PSP operation. In Slave mode, the port is asynchronously readable and writable by the external world. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting the control bit PSPMODE enables the PORTE I/O pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input, and RE2 is the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The timing for the control signals in write and read modes is shown in Figure 10-2 and Figure 10-3, respectively. Data Bus D WR LATD or WR PORTD CK Data Latch Q RD PORTD D EN EN TTL Q RDx pin RD LATD Set Interrupt Flag PSPIF (PIR1<7>) PORTE pins Read RD TTL Chip Select TTL Write TTL Note: I/O pins have diode protection to VDD and VSS. CS WR FIGURE 10-2: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF 2002 Microchip Technology Inc. Preliminary DS41159B-page 105 PIC18FXX8 FIGURE 10-3: PARALLEL SLAVE PORT READ WAVEFORMS Q1 CS WR RD PORTD IBF OBF PSPIF Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TABLE 10-1: Name PORTD LATD TRISD PORTE LATE TRISE INTCON PIR1 PIE1 IPR1 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS Bit 7 Port Data Latch when written; Port pins when read LATD Data Output bits PORTD Data Direction bits -- IBF PSPIF PSPIE PSPIP -- OBF ADIF ADIE ADIP -- IBOV RCIF RCIE RCIP -- PSPMODE INT0IE TXIF TXIE TXIP -- -- RBIE SSPIF SSPIE SSPIP RE2 RE1 RE0 LATE Data Output bits PORTE Data Direction bits TMR0IF INT0IF RBIF GIE/GIEH PEIE/GIEL TMR0IE xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 ---- -000 ---- -000 ---- -xxx ---- -uuu 0000 -111 0000 -111 0000 000x 0000 000u CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. DS41159B-page 106 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 11.0 TIMER0 MODULE Register 11-1 shows the Timer0 Control register (T0CON). Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. Note: Timer0 is enabled on POR. The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode, and FFFFh to 0000h in 16-bit mode * Edge select for external clock REGISTER 11-1: T0CON REGISTER R/W-1 TMR0ON bit 7 R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2-0 2002 Microchip Technology Inc. Preliminary DS41159B-page 107 PIC18FXX8 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus 1 RA4/T0CKI pin(2) T0SE FOSC/4 0 Programmable Prescaler 0 8 1 Sync with Internal Clocks (2 TCY delay) TMR0L 3 T0PS2, T0PS1, T0PS0 T0CS(1) PSA Set Interrupt Flag bit TMR0IF on Overflow Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. FIGURE 11-2: T0CKI pin(2) TIMER0 BLOCK DIAGRAM IN 16-BIT MODE 1 T0SE FOSC/4 0 Programmable Prescaler 3 T0PS2, T0PS1, T0PS0 T0CS(1) PSA 8 8 TMR0H 8 Data Bus<7:0> Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. 0 1 Sync with Internal Clocks (2 TCY delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow Read TMR0L Write TMR0L DS41159B-page 108 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 11.1 Timer0 Operation 11.2.1 Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0L register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). 11.3 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP. 11.4 16-bit Mode Timer Reads and Writes 11.2 Prescaler Timer0 can be set in 16-bit mode by clearing T0CON T08BIT. Registers TMR0H and TMR0L are used to access 16-bit timer value. TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-1). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of buffered value of TMR0H, when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF TMR0, MOVWF TMR0, BSF TMR0, x.... etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment. TABLE 11-1: Name TMR0L TMR0H INTCON T0CON TRISA Bit 7 REGISTERS ASSOCIATED WITH TIMER0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx 0000 0000 Value on all other RESETS uuuu uuuu 0000 0000 0000 000u 1111 1111 --11 1111 Timer0 Module Low Byte Register Timer0 Module High Byte Register GIE/GIEH TMR0ON -- PEIE/GIEL T08BIT TMR0IE T0CS INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 0000 000x 1111 1111 --11 1111 PORTA Data Direction Register(1) Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read as `0'. 2002 Microchip Technology Inc. Preliminary DS41159B-page 109 PIC18FXX8 NOTES: DS41159B-page 110 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * RESET from CCP module special event trigger Register 12-1 shows the Timer1 control register. This register controls the Operating mode of the Timer1 module as well as contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON register). Figure 12-1 is a simplified block diagram of the Timer1 module. Note: Timer1 is disabled on POR. REGISTER 12-1: T1CON REGISTER R/W-0 RD16 bit 7 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 T1CKPS1 T1CKPS0 T1OSCEN bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 6 bit 5-4 bit 3 bit 2 bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 111 PIC18FXX8 12.1 Timer1 Operation Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The Operating mode is determined by the clock select bit, TMR1CS (T1CON register). When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "RESET input". This RESET can be generated by the CCP module (Section 15.1). FIGURE 12-1: TMR1IF Overflow Interrupt Flag bit TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1 TMR1H CLR TMR1L TMR1ON On/Off T1OSC 0 1 T1SYNC Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP Input Synchronize det Synchronized Clock Input T13CKI/T1OSO T1OSI T1OSCEN Enable Oscillator(1) 1 FOSC/4 Internal Clock Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8 Timer 1 high byte TMR1 TMR1L 1 TMR1ON On/Off T1OSC T13CKI/T1OSO T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock 1 Prescaler 1, 2, 4, 8 0 2 TMR1CS T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. SLEEP Input Synchronize det T1SYNC Special Event Trigger 0 Synchronized Clock Input 8 T1OSI DS41159B-page 112 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 12.2 Timer1 Oscillator 12.4 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON register). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. Resetting Timer1 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = `1011'), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR registers). TABLE 12-1: CAPACITOR SELECTION FOR THE ALTERNATE OSCILLATOR Freq 32 kHz C1 TBD(1) C2 TBD(1) 20 PPM Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair, effectively becomes the period register for Timer1. Osc Type LP Crystal to be Tested: 32.768 kHz Epson C-001R32.768K-A 12.5 Timer1 16-bit Read/Write Mode Note 1: Microchip suggests 33 pF as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON register) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1, without having to determine whether a read of the high byte, followed by a read of the low byte is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 12.3 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR registers). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE registers). TABLE 12-2: Name Bit 7 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR1L TMR1H T1CON Legend: PSPIF PSPIE PSPIP ADIF ADIE ADIP 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2002 Microchip Technology Inc. Preliminary DS41159B-page 113 PIC18FXX8 NOTES: DS41159B-page 114 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 13.0 * * * * * * * TIMER2 MODULE 13.1 Timer2 Operation The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON Register). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, PIR registers). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device RESET (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. Note: Timer2 is disabled on POR. Register 13-1 shows the Timer2 Control register. Timer2 can be shut-off by clearing control bit TMR2ON (T2CON register) to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register. REGISTER 13-1: T2CON REGISTER U-0 -- bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR2ON R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 T2CKPS1 T2CKPS0 bit 7 bit 6-3 Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 2 bit 1-0 2002 Microchip Technology Inc. Preliminary DS41159B-page 115 PIC18FXX8 13.2 Timer2 Interrupt 13.3 Output of TMR2 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The output of TMR2 (before the postscaler) is a clock input to the Synchronous Serial Port module, which optionally uses it to generate the shift clock. FIGURE 13-1: TIMER2 BLOCK DIAGRAM TMR2 Output(1) Sets Flag bit TMR2IF FOSC/4 Prescaler 1:1, 1:4, 1:16 2 T2CKPS1:T2CKPS0 TMR2 RESET Comparator EQ PR2 Postscaler 1:1 to 1:16 4 TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. TABLE 13-1: Name Bit 7 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR2 T2CON PR2 PSPIF PSPIE PSPIP -- ADIF ADIE ADIP 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 Timer2 Module Register Timer2 Period Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. DS41159B-page 116 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control Register. This register controls the Operating mode of the Timer3 module and sets the CCP1 and ECCP1 clock source. Register 12-1 shows the Timer1 Control register. This register controls the Operating mode of the Timer1 module, as well as contains the Timer1 oscillator enable bit (T1OSCEN), which can be a clock source for Timer3. Note: Timer3 is disabled on POR. The Timer3 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers: TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * RESET from CCP1/ECCP1 module trigger REGISTER 14-1: T3CON REGISTER R/W-0 RD16 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 T3CCP1 R/W-0 T3SYNC R/W-0 TMR3CS R/W-0 TMR3ON bit 0 T3ECCP1 T3CKPS1 T3CKPS0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP1/ECCP1 Enable bits 1x =Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules 01 =Timer3 is the clock source for compare/capture of ECCP1, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture CCP1 and ECCP1 modules T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6,3 bit 5-4 bit 2 bit 1 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 117 PIC18FXX8 14.1 Timer3 Operation Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The Operating mode is determined by the clock select bit, TMR3CS (T3CON register). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input, or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer3 also has an internal "RESET input". This RESET can be generated by the CCP module (Section 15.1). FIGURE 14-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H CCP Special Trigger T3CCPx 0 CLR TMR3L TMR3ON On/Off T1OSC 1 T3SYNC Synchronize det Synchronized Clock Input T1OSO/ T13CKI T1OSI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 TMR3CS T3CKPS1:T3CKPS0 SLEEP Input Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 Write TMR3L Read TMR3L TMR3IF Overflow Interrupt Flag bit 8 TMR3H TMR3 TMR3L CLR 1 To Timer1 Clock Input T1OSO/ T13CKI T1OSC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 0 2 T3CKPS1:T3CKPS0 TMR3CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. SLEEP Input TMR3ON On/Off T3SYNC Synchronize det CCP Special Trigger T3CCPx 0 Synchronized Clock Input 8 T1OSI DS41159B-page 118 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN bit (T1CON Register). The oscillator is a low power oscillator rated up to 200 kHz. Refer to Section 12.0, Timer1 Module for Timer1 oscillator details. Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. Note: The special event triggers from the CCP module will not set interrupt flag bit TMR3IF (PIR registers). 14.3 Timer3 Interrupt The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR3IF (PIR registers). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit TMR3IE (PIE registers). Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair becomes the period register for Timer3. Refer to Section 15.0, "Capture/Compare/PWM (CCP) Modules for CCP details. TABLE 14-1: Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON Legend: Bit 7 REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 6 Bit 5 TMR0IE -- -- -- Bit 4 INT0IE EEIF EEIE EEIP Bit 3 RBIE BCLIF BCLIE BCLIP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF Bit 0 RBIF Value on POR, BOR Value on all other RESETS GIE/ GIEH PEIE/GIEL -- -- -- CMIF CMIE CMIP 0000 000x 0000 000u TMR3IF ECCP1IF -0-0 0000 -0-0 0000 TMR3IE ECCP1IE -0-0 0000 -0-0 0000 TMR3IP ECCP1IP -0-0 0000 -0-0 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 RD16 -- T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2002 Microchip Technology Inc. Preliminary DS41159B-page 119 PIC18FXX8 NOTES: DS41159B-page 120 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES received time stamp for the CAN module (refer to Section 19.0, CAN Module for CAN operation), which the ECCP module does not. The ECCP module, on the other hand, has enhanced PWM functionality and auto shutdown capability. Aside from these, the operation of the module described in the this section is the same as the ECCP . The control register for the CCP module is shown in Register 15-1. Table 15-2 (following page) details the interactions of the CCP and ECCP modules. The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM Duty Cycle register. The operation of the CCP module is identical to that of the ECCP module (discussed in detail in Section 16.0), with two exceptions. The CCP module has a Capture special event trigger that can be used as a message REGISTER 15-1: CCP1CON REGISTER U-0 -- bit 7 U-0 -- R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0 bit 7-6 bit 5-4 Unimplemented: Read as '0' DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0 Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Capture mode, CAN message received (CCP1 only) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set) 1001 = Compare mode, initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set) 1010 = Compare mode, CCP pin is unaffected (CCPIF bit is set) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP resets TMR1 or TMR3 and starts an A/D conversion, if the A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 3-0 2002 Microchip Technology Inc. Preliminary DS41159B-page 121 PIC18FXX8 15.1 CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. Table 15-1 shows the timer resources of the CCP module modes. An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR registers) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 15.2.1 CCP PIN CONFIGURATION TABLE 15-1: CCP1 MODE - TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. CCP1 Mode Capture Compare PWM 15.2.2 TIMER1/TIMER3 MODE SELECTION 15.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on pin RC2/CCP1. An event is defined as: * * * * every falling edge every rising edge. every 4th rising edge every 16th rising edge The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. TABLE 15-2: CCP1 Mode Capture Capture Compare PWM PWM PWM INTERACTION OF CCP1 AND ECCP1 MODULES ECCP1 Mode Capture Compare Compare PWM Capture Compare Interaction TMR1 or TMR3 time-base. Time-base can be different for each CCP. The compare could be configured for the special event trigger, which clears either TMR1 or TMR3, depending upon which time-base is used. The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3, depending upon which time-base is used. The PWMs will have the same frequency and update rate (TMR2 interrupt). None. None. DS41159B-page 122 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 15.2.3 SOFTWARE INTERRUPT 15.2.5 CAN MESSAGE TIME-STAMP When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE registers) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in Operating mode. The CAN capture event occurs when a message is received in either of the receive buffers. The CAN module provides a rising edge to the CCP1 module to cause a capture event. This feature is provided to time-stamp the received CAN messages. This feature is enabled by setting the CANCAP bit of the CAN I/O control register (CIOCON<4>). The message receive signal from the CAN module then takes the place of the events on RC2/CCP1. 15.2.4 CCP1 PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP1 module is turned off, or the CCP1 module is not in Capture mode, the prescaler counter is cleared. This means that any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 15-1: CLRF MOVLW CHANGING BETWEEN CAPTURE PRESCALERS ; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value CCP1CON, F NEW_CAPT_PS MOVWF CCP1CON FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF (PIR1<2>) T3CCP1 T3ECCP1 Prescaler / 1, 4, 16 CCP1 pin and Edge Detect TMR3H TMR3 Enable CCPR1H TMR1 Enable T3ECCP1 T3CCP1 TMR1H TMR1L CCPR1L TMR3L CCP1CON<3:0> Qs Note: I/O pins have diode protection to VDD and VSS. 2002 Microchip Technology Inc. Preliminary DS41159B-page 123 PIC18FXX8 15.3 Compare Mode 15.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 and ECCPR1 register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the CCP1 pin can have one of the following actions: * * * * Driven high Driven low Toggle output (high to low or low to high) Remains unchanged Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 15.3.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). The action on the pin is based on the value of control bits CCP1M3:CCP1M0. At the same time, interrupt flag bit CCP1IF is set. 15.3.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets either the TMR1 or TMR3 register pair. Additionally, the ECCP1 Special Event Trigger will start an A/D conversion, if the A/D module is enabled. Note: The Special Event Trigger from the ECCP1 module will not set the Timer1 or Timer3 interrupt flag bits. 15.3.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the appropriate TRISC bit. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the data latch. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit) Set bit GO/DONE, which starts an A/D conversion (ECCP1 only) TMR1H Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) TMR1L TMR3H TMR3L T3CCP1 T3ECCP1 0 1 Q CCP1 Output Enable S R Output Logic Match Comparator CCPR1H CCPR1L CCP1CON<3:0> Mode Select Note: I/O pins have diode protection to VDD and VSS. DS41159B-page 124 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 15-3: Name INTCON PIR1 PIE1 IPR1 TRISD TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON PIR2 PIE2 IPR2 TMR3L TMR3H T3CON Legend: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS GIE/ GIEH PSPIF PSPIE PSPIP 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTD Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- -- -- -- CMIF CMIE CMIP DC1B1 -- -- -- DC1B0 EEIF EEIE EEIP CCP1M3 BCLIF BCLIE BCLIP CCP1M2 LVDIF LVDIE LVDIP CCP1M1 TMR3IF TMR3IE TMR3IP TMR1ON 0-00 0000 u-uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 --00 0000 --00 0000 ECCP1IF -0-0 0000 -0-0 0000 ECCP1IE -0-0 0000 -0-0 0000 ECCP1IP -0-0 0000 -0-0 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. 2002 Microchip Technology Inc. Preliminary DS41159B-page 125 PIC18FXX8 15.4 PWM Mode 15.4.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula. EQUATION 15-1: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 13.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Figure 15-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.4.3. FIGURE 15-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L (Master) CCPR1H (Slave) Q RC2/CCP1 TMR2 (Note 1) S Comparator Clear Timer, Set CCP1 pin and latch D.C. TRISC<2> 15.4.2 R PWM DUTY CYCLE Comparator The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time. PR2 EQUATION 15-2: PWM duty cycle =(CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit time-base. A PWM output (Figure 15-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 15-4: Period PWM OUTPUT Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS41159B-page 126 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. 15.4.3 SETUP FOR PWM OPERATION EQUATION 15-3: FOSC log --------------- FPWM PWM Resolution (max) = -----------------------------bits log ( 2 ) The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. 4. 5. TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 2.44 kHz 16 FFh 10 9.76 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.3 kHz 1 3Fh 8 312.5 kHz 1 1Fh 7 416.6 kHz 1 17h 5.5 PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 15-5: Name INTCON PIR1 PIE1 IPR1 TRISD TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON Legend: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 GIE/ GIEH Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 PSPIF PSPIE PSPIP PORTD Data Direction Register Timer2 Module Register Timer2 Module Period Register -- Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 --00 0000 --00 0000 x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. 2002 Microchip Technology Inc. Preliminary DS41159B-page 127 PIC18FXX8 NOTES: DS41159B-page 128 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The ECCP (Enhanced Capture/Compare/ PWM) module is only available on PIC18F448 and PIC18F458 devices. The operation of the ECCP module differs from the CCP (discussed in detail in Section 15.0) with the addition of an enhanced PWM module, which allows for up to 4 output channels and user selectable polarity. These features are discussed in detail in Section 16.5. The module can also be programmed for automatic shutdown in response to various analog or digital events. The control register Register 16-1. for ECCP1 is shown in Note: This module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register, or a PWM Master/Slave Duty Cycle register. REGISTER 16-1: ECCP1CON REGISTER R/W-0 R/W-0 EPWM1M1 EPWM1M0 bit 7 R/W-0 EDC1B1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 bit 0 bit 7-6 bit 5-4 bit 3-0 EPWM1M<1:0>: PWM Output Configuration bits If ECCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If ECCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output; P1A, P1B modulated with deadband control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive EDC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in ECCPR1L. ECCP1M<3:0>: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (ECCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (ECCP1IF bit is set) 1001 = Compare mode, clear output on match (ECCP1IF bit is set) 1010 = Compare mode, ECCP1 pin is unaffected (ECCP1IF bit is set) 1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1or TMR3, and starts an A/D conversion, if the A/D module is enabled) 1100 = PWM mode; P1A, P1C active high; P1B, P1D active high 1101 = PWM mode; P1A, P1C active high; P1B, P1D active low 1110 = PWM mode; P1A, P1C active low; P1B, P1D active high 1111 = PWM mode; P1A, P1C active low; P1B, P1D active low Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 129 PIC18FXX8 16.1 ECCP1 Module Enhanced Capture/Compare/PWM Register1 (ECCPR1) is comprised of two 8-bit registers: ECCPR1L (low byte) and ECCPR1H (high byte). The ECCP1CON register controls the operation of ECCP1; the additional registers, ECCPAS and ECCP1DEL, control enhanced PWM specific features. All registers are readable and writable. Table 16-1 shows the timer resources for the ECCP module modes. Table 16-2 describes the interactions of the ECCP module with the standard CCP module. In PWM mode, the ECCP module can have up to four available outputs, depending on which Operating mode is selected. These outputs are multiplexed with PORTD and the Parallel Slave Port. Both the Operating mode and the output pin assignments are configured by setting PWM Output Configuration bits EPWM1M1:EPWM1M0 (ECCP1CON<7:6>). The specific pin assignments for the various Output modes are shown in Table 16-3. TABLE 16-1: ECCP1 MODE - TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 ECCP1 Mode Capture Compare PWM TABLE 16-2: ECCP1 Mode Capture Capture Compare PWM PWM PWM INTERACTION OF CCP1 AND ECCP1 MODULES CCP1 Mode Capture Compare Compare PWM Capture Compare Interaction TMR1 or TMR3 time-base. Time-base can be different for each CCP. The compare could be configured for the special event trigger, which clears either TMR1 or TMR3, depending upon which time-base is used. The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3 depending upon which time-base is used. The PWMs will have the same frequency and update rate (TMR2 interrupt). None None TABLE 16-3: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES ECCP1CON Configuration 00xx11xx 10xx11xx x1xx11xx RD4 ECCP1 P1A P1A RD5 RD<5>, PSP<5> P1B P1B RD6 RD<6>, PSP<6> RD<6>, PSP<6> P1C RD7 RD<7>, PSP<7> RD<7>, PSP<7> P1D ECCP Mode(1) Conventional CCP Compatible Dual Output PWM(2) Quad Output PWM(2) Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: In all cases, the appropriate TRISD bits must be cleared to make the corresponding pin an output. 2: In these modes, the PSP I/O control for PORTD is overridden by P1B, P1C and P1D. DS41159B-page 130 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 16.2 Capture Mode 16.3 Compare Mode The Capture Mode of the ECCP module is virtually identical in operation to that of the standard CCP module, as discussed in Section 15.1. The differences are in the registers and port pins involved: * The 16-bit Capture register is ECCPR1 (ECCPR1H and ECCPR1L); * The capture event is selected by control bits ECCP1M3:ECCP1M0 (ECCP1CON<3:0>); * The interrupt bits are ECCP1IE (PIE2<0>) and ECCP1IF (PIR2<0>); and * The capture input pin is RD4, and its corresponding direction control bit is TRISD<4>. Other operational details, including timer selection, output pin configuration and software interrupts, are exactly the same as the standard CCP module. The Compare Mode of the ECCP module is virtually identical in operation to that of the standard CCP module, as discussed in Section 15.2. The differences are in the registers and port pins, as described in Section 16.2. All other details are exactly the same. 16.3.1 SPECIAL EVENT TRIGGER Except as noted below, the special event trigger output of ECCP1 functions identically to that of the standard CCP module. It may be used to start an A/D conversion if the A/D module is enabled. Note: The special Event trigger from the ECCP1 module will not set the Timer1 or Timer3 interrupt flag bits. 16.2.1 CAN MESSAGE TIME-STAMP The special capture event for the reception of CAN messages (Section 15.2.5) is not available with the ECCP module. TABLE 16-4: REGISTERS ASSOCIATED WITH ENHANCED CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 Bit 4 INT0IE EEIF EEIE EEIP Bit 3 RBIE BCLIF BCLIE BCLIP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF Value on POR, BOR Value on all other RESETS Name INTCON PIR2 PIE2 IPR2 TMR1L TMR1H T1CON TMR3L TMR3H T3CON TRISD ECCPR1L ECCPR1H GIE/GIEH PEIE/GIEL TMR0IE -- -- -- CMIF CMIE CMIP -- -- -- 0000 000x 0000 000u ECCP1IF -0-0 0000 -0-0 0000 ECCP1IE -0-0 0000 -0-0 0000 ECCP1IP -0-0 1111 -1-1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC PORTD Data Direction Register Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) EDC1B0 TMR1CS TMR1ON 0-00 0000 u-uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR3CS TMR3ON 0000 0000 uuuu uuuu 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the ECCP module and Timer1. 2002 Microchip Technology Inc. Preliminary DS41159B-page 131 PIC18FXX8 16.4 Standard PWM Mode When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode, as described in Section 15.4. The differences in registers and ports are as described in Section 16.2; in addition, the two Least Significant bits of the 10-bit PWM duty cycle value are represented by ECCP1CON<5:4>. Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 15.4.3 or Section 16.5.8. The latter is more generic, but will work for either single or multi-output PWM. Figure 16-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when the assigned timer resets), in order to prevent glitches on any of the outputs. The exception is the PWM delay register ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets, instead of starting immediately. This means that enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRISD bits for output. 16.5 Enhanced PWM Mode 16.5.1 PWM OUTPUT CONFIGURATIONS The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and is modified to provide up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active high or active low). The module's Output mode and polarity are configured by setting the EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits of the ECCP1CON register (ECCP1CON<7:6> and ECCP1CON<3:0>, respectively). The EPWM1M<1:0> bits in the ECCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode The Single Output mode is the Standard PWM mode discussed in Section 15.4. The Half-Bridge and FullBridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 16-2. FIGURE 16-1: Duty Cycle Registers ECCPR1L SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE ECCP1CON<5:4> EPWM1M1<1:0> 2 ECCP1M<3:0> 4 ECCP1/P1A TRISD<4> ECCPR1H (Slave) P1B R Q Output Controller P1C TMR2 (Note 1) S P1D Clear Timer, set ECCP1 pin and latch D.C. ECCP1DEL TRISD<7> TRISD<6> TRISD<5> RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B Comparator RD6/PSP6/P1C Comparator RD7/PSP7/P1D PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time-base. DS41159B-page 132 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS 0 ECCP1CON <7:6> SIGNAL DUTY CYCLE PERIOD PR2+1 P1A Modulated, Active High 00 P1A Modulated, Active Low P1A Modulated, Active High P1A Modulated, Active Low 10 P1B Modulated, Active High P1B Modulated, Active Low P1A Active, Active High P1A Active, Active Low P1B Inactive, Active High P1B Inactive, Active Low 01 P1C Inactive, Active High P1C Inactive, Active Low P1D Modulated, Active High P1D Modulated, Active Low P1A Inactive, Active High P1A Inactive, Active Low P1B Modulated, Active High P1B Modulated, Active Low 11 P1C Active, Active High P1C Active, Active Low P1D Inactive, Active High P1D Inactive, Active Low Delay Delay Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value) * Delay = 4 * TOSC * ECCP1DEL 2002 Microchip Technology Inc. Preliminary DS41159B-page 133 PIC18FXX8 16.5.2 HALF-BRIDGE MODE FIGURE 16-3: Period Duty Cycle P1A(2) td P1B(2) (1) In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The RD4/PSP4/ ECCP1/P1A pin has the PWM output signal, while the RD5/PSP5/P1B pin has the complementary PWM output signal (Figure 16-3). This mode can be used for half-bridge applications, as shown in Figure 16-4, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in bridge power devices. The value of register ECCP1DEL dictates the number of clock cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 16.5.4 for more details of the deadband delay operations. Since the P1A and P1B outputs are multiplexed with the PORTD<4> and PORTD<5> data latches, the TRISD<4> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. HALF-BRIDGE PWM OUTPUT Period td (1) (1) td = Deadband Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as asserted high. FIGURE 16-4: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") PIC18F448/458 P1A FET Driver + V + Load - FET Driver P1B + V - VHalf-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F448/458 FET Driver P1A + FET Driver P1B Load FET Driver FET Driver V- DS41159B-page 134 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 16.5.3 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RD4/PSP4/ECCP1/P1A is continuously active, and pin RD7/PSP7/P1D is modulated. In the Reverse mode, RD6/PSP6/P1C pin is continuously active, and RD5/PSP5/P1B pin is modulated. These are illustrated in Figure 16-5. P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4:7> data latches. The TRISD<4:7> bits must be cleared to make the P1A, P1B, P1C, and P1D pins output. FIGURE 16-5: FORWARD MODE FULL-BRIDGE PWM OUTPUT Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) REVERSE MODE Period Duty Cycle P1A (2) (1) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as asserted high. 2002 Microchip Technology Inc. Preliminary DS41159B-page 135 PIC18FXX8 FIGURE 16-6: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F448/458 P1D FET Driver QD QB FET Driver + P1C FET Driver Load FET Driver P1B QC QA VP1A 16.5.3.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the ECCP1CON register allows user to control the Forward/Reverse direction. When the application firmware changes this direction control bit, the ECCP1 module will assume the new direction on the next PWM cycle. The current PWM cycle still continues, however, the non-modulated outputs, P1A and P1C signals, will transition to the new direction TOSC, 4 TOSC or 16 TOSC earlier (for T2CKRS<1:0> = 00, 01 or 1x, respectively), before the end of the period. During this transition cycle, the modulated outputs, P1B and P1D, will go to the inactive state (Figure 16-7). Note that in the Full-Bridge Output mode, the ECCP module does not provide any deadband delay. In general, since only one output is modulated at all times, deadband delay is not required. However, there is a situation where a deadband delay might be required. This situation occurs when all of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than turn on time. Figure 16-8 shows an example where the PWM direction changes from forward to reverse, at a near 100% duty cycle. At time t1, the output P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn off time of the power devices is longer than the turn on time, a shoot-through current flows through power devices QB and QD (see Figure 16-6) for the duration of `t'. The same phenomenon will occur to power devices QA and QC for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Avoid changing PWM output direction at or near 100% duty cycle. Use switch drivers that compensate the slow turn off of the power devices. The total turn off time (toff) of the power device and the driver must be less than the turn on time (ton). DS41159B-page 136 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 16-7: SIGNAL DC P1A (Active High) P1B (Active High) P1C (Active High) P1D (Active High) (2) PWM DIRECTION CHANGE PERIOD (1) PERIOD Note 1: The direction bit in the ECCP1 Control Register (ECCP1CON.EPWM1M1) is written any time during the PWM cycle. 2: The P1A and P1C signals switch at intervals of TOSC, 4 TOSC or 16 TOSC, depending on the Timer2 prescaler value earlier when changing direction. The modulated P1B and P1D signals are inactive at this time. FIGURE 16-8: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE FORWARD PERIOD REVERSE PERIOD P1A P1B P1C P1D (PWM) (PWM) ton External Switch C toff External Switch D Potential Shoot-Through Current t = toff - ton t1 Note 1: All signals are shown as active high. 2: ton is the Turn-on Delay of power switch and driver. 3: toff is the Turn-off Delay of power switch and driver. 2002 Microchip Technology Inc. Preliminary DS41159B-page 137 PIC18FXX8 16.5.4 PROGRAMMABLE DEADBAND DELAY devices in the off state, until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). In half-bridge or full-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require longer time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches will be on for a short period of time until one switch completely turns off. During this time, a very high current (shoot-through current) flows through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on the power switch is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable deadband delay is available to avoid shootthrough current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 16-3 for illustration. The ECCP1DEL register (Register 16-2) sets the amount of delay. 16.5.6 START-UP CONSIDERATIONS Prior to enabling the PWM outputs, the P1A, P1B, P1C and P1D latches may not be in the proper states. Enabling the TRISD bits for output at the same time with the ECCP1 module may cause damage to the power switch devices. The ECCP1 module must be enabled in the proper Output mode with the TRISD bits enabled as inputs. Once the ECCP1 completes a full PWM cycle, the P1A, P1B, P1C and 1PD output latches are properly initialized. At this time, the TRISD bits can be enabled for outputs to start driving the power switch devices. The completion of a full PWM cycle is indicated by the TMR2IF bit going from a '0' to a '1'. 16.5.7 OUTPUT POLARITY CONFIGURATION The ECCP1M<1:0> bits in the ECCP1CON register allow user to choose the logic conventions (asserted high/low) for each of the outputs. The PWM output polarities must be selected before the PWM outputs are enabled. Charging the polarity configuration while the PWM outputs are active is not recommended, since it may result in unpredictable operation. 16.5.5 SYSTEM IMPLEMENTATION When the ECCP module is used in the PWM mode, the application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins. When the microcontroller powers up, all of the I/O pins are in the high-impedance state. The external pull-up and pull-down resistors must keep the power switch REGISTER 16-2: ECCP1DEL REGISTER R/W-0 EPDC7 bit 7 R/W-0 EPDC6 R/W-0 EPDC5 R/W-0 EPDC4 R/W-0 EPDC3 R/W-0 EPDC2 R/W-0 EPDC1 R/W-0 EPDC0 bit 0 bit 7-0 EPDC<7:0>: PWM Delay Count for Half-Bridge Output Mode bits Number of FOSC/4 (TOSC*4) cycles between the P1A transition and the P1B transition Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 138 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 16.5.8 SETUP FOR PWM OPERATION 2. The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. Configure the PWM module: a) Disable the ECCP1/P1A, P1B, P1C and/or P1D outputs by setting the respective TRISD bits. b) Set the PWM period by loading the PR2 register. c) Set the PWM duty cycle by loading the ECCPR1L register and ECCP1CON<5:4> bits. d) Configure the ECCP1 module for the desired PWM operation, by loading the ECCP1CON register with the appropriate value. With the ECCP1M<3:0> bits, select the active high/low levels for each PWM output. With the EPWM1M<1:0> bits, select one of the available Output modes. e) For Half-Bridge Output mode, set the deadband delay by loading the ECCP1DEL register with the appropriate value. Configure and start TMR2: a) Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit in the PIR1 register. b) Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). c) Enable Timer2 by setting the TMR2ON bit (T2CON<2>) register. Enable PWM outputs after a new cycle has started: a) Wait until TMR2 overflows (TMR2IF bit becomes a '1'). The new PWM cycle begins here. b) Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISD bits. 3. TABLE 16-5: Name INTCON RCON IPR2 PIR2 PIE2 TMR2 PR2 T2CON TRISD ECCPR1H ECCPR1L ECCPAS ECCP1DEL Legend: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Bit 6 PEIE/GIEL -- CMIP CMIF CMIE Bit 5 TMR0IE -- -- -- -- Bit 4 INT0IE RI EEIP EEIF EEIE Bit 3 RBIE TO BCLIP BCLIF BCLIE Bit 2 TMR0IF PD LVDIP LVDIF LVDIE Bit 1 INT0IF POR TMR3IP TMR3IF TMR3IE Bit 0 RBIF BOR Value on POR, BOR Value on all other RESETS Bit 7 GIE/GIEH IPEN -- -- -- 0000 000x 0000 000u 0--1 11qq 0--q qquu ECCP1IP -0-0 1111 -1-1 1111 ECCP1IF -0-0 0000 -0-0 0000 ECCP1IE -0-0 0000 -0-0 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Timer2 Module Register Timer2 Module Period Register -- TOUTPS3 PORTD Data Direction Register Enhanced Capture/Compare/PWM Register1 High Byte Enhanced Capture/Compare/PWM Register1 Low Byte EDC1B1 EPDC5 EDC1B0 EPDC4 ECCPASE ECCPAS2 EPDC7 EPDC6 ECCPAS1 ECCPAS0 PSSAC1 EPDC3 PSSAC0 EPDC2 PSSBD1 EPDC1 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 ECCP1CON EPWM1M1 EPWM1M0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000 PSSBD0 0000 0000 0000 0000 EPDC0 0000 0000 uuuu uuuu x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the ECCP module. 2002 Microchip Technology Inc. Preliminary DS41159B-page 139 PIC18FXX8 16.6 Enhanced CCP Auto-Shutdown When the ECCP is programmed for any of the PWM modes, the output pins associated with its function may be configured for Auto-Shutdown. Auto-Shutdown allows the internal output of either of the two comparator modules, or the external interrupt 0, to asynchronously disable the ECCP output pins. Thus, an external analog or digital event can discontinue an ECCP sequence. The comparator output(s) to be used is selected by setting the proper mode bits in the ECCPAS register. To use external interrupt INT0 as a shutdown event, INT0IE must be set. To use either of the comparator module outputs as a shutdown event, corresponding comparators must be enabled. When a shutdown occurs, the selected output values (PSSACn, PSSBDn) are written to the ECCP port pins. The internal shutdown signal is gated with the outputs and will immediately and asynchronously disable the outputs. If the internal shutdown is still in effect at the time a new cycle begins, that entire cycle is suppressed, thus eliminating narrow, glitchy pulses. The ECCPASE bit is set by hardware upon a comparator event and can only be cleared in software. The ECCP outputs can be re-enabled only by clearing the ECCPASE bit. The Auto-Shutdown mode can be manually entered by writing a `1' to the ECCPASE bit. REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN CONTROL REGISTER R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1 R/W-0 PSSBD0 bit 0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs enabled, no shutdown event 1 = A shutdown event has occurred, must be reset in software to re-enable ECCP ECCPAS<2:0>: ECCP Auto-Shutdown bits 000 = No Auto-Shutdown enabled, comparators have no effect on ECCP 001 = Comparator 1 output will cause shutdown 010 = Comparator 2 output will cause shutdown 011 = Either Comparator 1 or 2 can cause shutdown 100 = INT0 101 = INT0 or Comparator 1 output 110 = INT0 or Comparator 2 output 111 = INT0 or Comparator 1 or Comparator 2 output PSSACn: Pin A and C Shutdown State Control bits 00 = Drive Pins A and C to `0' 01 = Drive Pins A and C to `1' 1x = Pins A and C tri-state PSSBDn: Pin B and D Shutdown State Control bits 00 = Drive Pins B and D to `0' 01 = Drive Pins B and D to `1' 1x = Pins B and D tri-state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6-4 bit 3-2 bit 1-0 DS41159B-page 140 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RF7/SS Figure 17-1 shows the block diagram of the MSSP module when operating in SPI mode. 17.1 The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode FIGURE 17-1: MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPBUF reg Write 17.2 Control Registers RC4/SDI/SDA SSPSR reg RC5/SDO bit0 Shift Clock The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. RF7/SS SS Control Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64 RC3/SCK/ SCL ( ) Data to TX/RX in SSPSR TRIS bit 2002 Microchip Technology Inc. Preliminary DS41159B-page 141 PIC18FXX8 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: * * * * MSSP Control Register1 (SSPCON1) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode CKE: SPI Clock Edge Select When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit Used in I2C mode only P: STOP bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. S: START bit Used in I2C mode only R/W: Read/Write bit information Used in I2C mode only UA: Update Address Used in I2C mode only BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 142 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE) R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 bit 6 bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = IDLE state for clock is a high level 0 = IDLE state for clock is a low level SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C mode only. bit 3-0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 143 PIC18FXX8 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (IDLE state of SCK) Data input sample phase (middle or end of data output time) * Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the * * * * SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER ;Has data been received(transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit LOOP BTFSS SSPSTAT, BF BRA LOOP MOVF SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF DS41159B-page 144 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISF<7> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data -- Slave sends dummy data * Master sends data -- Slave sends data * Master sends dummy data -- Slave sends data FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SDO SDI SPI Slave SSPM3:SSPM0 = 010xb Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb SDI SDO Shift Register (SSPSR) MSb LSb SCK PROCESSOR 1 Serial Clock SCK PROCESSOR 2 2002 Microchip Technology Inc. Preliminary DS41159B-page 145 PIC18FXX8 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 17-3, Figure 17-5, and Figure 17-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 17-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 17-3: Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF SPI MODE WAVEFORM (MASTER MODE) 4 Clock Modes bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 bit7 bit0 bit7 bit0 Next Q4 cycle after Q2 DS41159B-page 146 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to 0. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. 17.3.7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The Data Latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit7 bit0 SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit0 bit7 bit7 Next Q4 cycle after Q2 2002 Microchip Technology Inc. Preliminary DS41159B-page 147 PIC18FXX8 FIGURE 17-5: SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) bit7 bit0 Next Q4 cycle after Q2 FIGURE 17-6: SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 Next Q4 cycle after Q2 DS41159B-page 148 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.3.8 SLEEP OPERATION 17.3.10 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the device to be placed in SLEEP mode and data to be shifted into the SPI transmit/receive shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device from SLEEP. Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 17-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1 17.3.9 EFFECTS OF A RESET A RESET disables the MSSP module and terminates the current transfer. There is also a SMP bit, which controls when the data is sampled. TABLE 17-2: Name INTCON PIR1 PIE1 IPR1 TRISC TRISF SSPBUF SSPCON SSPSTAT REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP TRISF5 SSPEN D/A Bit 4 INT0IE TXIF TXIE TXIP TRISF4 CKP P Bit 3 RBIE SSPIF SSPIE SSPIP TRISF3 SSPM3 S Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP TRISF2 SSPM2 R/W Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TRISF1 SSPM1 UA Bit 0 RBIF TMR1IF TMR1IE TMR1IP TRISF0 SSPM0 BF Value on POR, BOR Value on all other RESETS GIE/GIEH PEIE/GIEL PSPIF PSPIE PSPIP TRISF7 WCOL SMP ADIF ADIE ADIP TRISF6 SSPOV CKE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 1111 0111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. 2002 Microchip Technology Inc. Preliminary DS41159B-page 149 PIC18FXX8 17.4 I2C Mode 17.4.1 REGISTERS The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCL) - RC3/SCK/SCL * Serial data (SDA) - RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The MSSP module has six registers for I2C operation. These are: MSSP Control Register1 (SSPCON1) MSSP Control Register2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) SSPCON, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the baud rate generator reload value. LSb * * * * * FIGURE 17-7: MSSP BLOCK DIAGRAM (I2C MODE) Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg Write RC3/SCK/SCL RC4/ SDI/ SDA MSb In receive operations, SSPSR and SSPBUF together, create a double buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Addr Match Match Detect SSPADD reg START and STOP bit Detect Set, Reset S, P bits (SSPSTAT reg) During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. DS41159B-page 150 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 SMP bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High Speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit 1 = Indicates that a STOP bit has been detected last 0 = STOP bit was not detected last Note: bit 3 This bit is cleared on RESET and when SSPEN is cleared. S: START bit 1 = Indicates that a START bit has been detected last 0 = START bit was not detected last Note: bit 2 This bit is cleared on RESET and when SSPEN is cleared. R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 6 bit 5 bit 4 In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: bit 1 ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 151 PIC18FXX8 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER1 (I2C MODE) R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave IDLE) 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved, or implemented in SPI mode only. bit 6 bit 5 bit 4 bit 3-0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 152 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: bit 4 Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0 bit 6 bit 5 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence IDLE RCEN: Receive Enable bit (Master Mode only) 1 = Enables Receive mode for I2C 0 = Receive IDLE PEN: STOP Condition Enable bit (Master mode only) 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition IDLE bit 3 bit 2 bit 1 RSEN: Repeated START Condition Enabled bit (Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition IDLE SEN: START Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition IDLE In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is enabled for Slave Transmit only (Legacy mode) Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). bit 0 Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 153 PIC18FXX8 17.4.2 OPERATION 17.4.3.1 Addressing The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * * * * I2C Master mode, clock = OSC/4 (SSPADD +1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled * I 2C Firmware controlled master operation, slave is IDLE Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The buffer full bit BF is set. An ACK pulse is generated. MSSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins. 17.4.3 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). Slave mode hardware will always generate an The I interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on START and STOP bits When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. * The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101. 2C In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. Receive first (high) byte of Address (bits SSPIF, BF and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 3. 4. 5. 6. 7. 8. 9. DS41159B-page 154 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.3.2 Reception 17.4.3.3 Transmission When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON1<0>=1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit CKP (SSPCON<4>). See Section 17.4.4, Clock Stretching for more detail. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low, regardless of SEN (see Section 17.4.4, Clock Stretching for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data.The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 17-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the START bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. 2002 Microchip Technology Inc. Preliminary DS41159B-page 155 FIGURE 17-8: DS41159B-page 156 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent. PIC18FXX8 SDA A7 A6 SCL S 1 2 SSPIF (PIR1<3>) I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 2002 Microchip Technology Inc. CKP (CKP does not reset to `0' when SEN = 0) FIGURE 17-9: 2002 Microchip Technology Inc. R/W = 1 ACK D1 D0 D4 D3 D5 D7 D6 A1 D3 D2 ACK D5 D4 D7 D6 D2 Transmitting Data Transmitting Data D1 D0 ACK A4 A2 A3 4 SCL held low while CPU responds to SSPIF 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software From SSPIF ISR SSPBUF is written in software SSPBUF is written in software Cleared in software From SSPIF ISR CKP is set in software CKP is set in software Receiving Address SDA A7 A6 A5 SCL 1 2 3 S Data in sampled SSPIF (PIR1<3>) I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) CKP PIC18FXX8 DS41159B-page 157 FIGURE 17-10: DS41159B-page 158 Clock is held low until update of SSPADD has taken place R/W = 0 ACK A7 D3 D2 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 ACK Clock is held low until update of SSPADD has taken place 0 A9 A8 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 6 7 8 9 P Bus Master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address PIC18FXX8 Receive First Byte of Address SDA 1 1 1 1 SCL S 1 2 3 4 SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) Preliminary SSPOV (SSPCON<6>) UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated 2002 Microchip Technology Inc. CKP (CKP does not reset to `0' when SEN = 0) FIGURE 17-11: Bus Master terminates transfer Clock is held low until CKP is set to `1' R/W=1 ACK Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK 2002 Microchip Technology Inc. Clock is held low until update of SSPADD has taken place R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address. CKP is set in software CKP is automatically cleared in hardware holding SCL low Receive First Byte of Address SDA 1 1 1 SCL S 1 2 3 SSPIF (PIR1<3>) I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Preliminary BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated CKP (SSPCON<4>) PIC18FXX8 DS41159B-page 159 PIC18FXX8 17.4.4 CLOCK STRETCHING 17.4.4.3 Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. Clock Stretching for 7-bit Slave Transmit Mode 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs, regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 17-9). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software, regardless of the state of the BF bit. 17.4.4.1 Clock Stretching for 7-bit Slave Receive Mode (SEN = 1) In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring. Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software, regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence, in order to prevent an overflow condition. 17.4.4.4 Clock Stretching for 10-bit Slave Transmit Mode In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence, which contains the high order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode, and clock stretching is controlled by the BF flag, as in 7-bit Slave Transmit mode (see Figure 17-11). 17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address, and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS41159B-page 160 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.4.5 Clock Synchronization and the CKP bit If a user clears the CKP bit, the SCL output is forced to `0'. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12). FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL CKP Master device asserts clock Master device de-asserts clock WR SSPCON 2002 Microchip Technology Inc. Preliminary DS41159B-page 161 FIGURE 17-13: DS41159B-page 162 Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent. PIC18FXX8 SDA A7 A6 SCL S 1 2 SSPIF (PIR1<3>) I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) Preliminary If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs BF (SSPSTAT<0>) SSPOV (SSPCON<6>) CKP CKP written to `1' in software 2002 Microchip Technology Inc. FIGURE 17-14: Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D0 D7 D6 D5 D4 ACK D3 D2 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte Clock is held low until update of SSPADD has taken place Clock is not held low because ACK = 1 ACK D1 D0 Receive First Byte of Address A9 A8 2002 Microchip Technology Inc. 6 1 2 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus Master terminates transfer Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock. UA is set indicating that SSPADD needs to be updated Note: Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock. An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set. CKP written to `1' in software SDA 1 1 1 1 0 SCL S 1 2 3 4 5 SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) Preliminary SSPOV (SSPCON<6>) UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated CKP PIC18FXX8 DS41159B-page 163 PIC18FXX8 17.4.5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0's with R/W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> set). Following a START bit detect, 8-bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 17-15). FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving data D6 D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF BF (SSPSTAT<0>) 1 General Call Address 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) '0' GCEN (SSPCON2<7>) '1' DS41159B-page 164 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.6 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is IDLE, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on START and STOP bit conditions. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a START condition on SDA and SCL. Assert a Repeated START condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a STOP condition on SDA and SCL. The MSSP Module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. The following events will cause SSP interrupt flag bit, SSPIF, to be set (SSP interrupt if enabled): * * * * * START condition STOP condition Data transfer byte transmitted/received Acknowledge Transmit Repeated START FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) DS41159B-page 165 Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0 SSPADD<6:0> SDA SDA in SCL SCL in Bus Collision START bit Detect STOP bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2) 2002 Microchip Technology Inc. Preliminary Clock Cntl START bit, STOP bit, Acknowledge Generate PIC18FXX8 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: 1. The user generates a START condition by setting the START enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out the SDA pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out the SDA pin until all 8 bits are transmitted. 9. The MSSP Module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a STOP condition by setting the STOP enable bit PEN (SSPCON2<2>). 12. Interrupt is generated once the STOP condition is complete. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 17.4.7, Baud Rate Generator for more details. DS41159B-page 166 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.7 I2C BAUD RATE GENERATOR In Master mode, the baud rate generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the baud rate generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 17-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 SCL Reload Control CLKO Reload BRG Down Counter FOSC/4 TABLE 17-3: FCY I2C CLOCK RATE W/BRG FCY*2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz BRG Value 19h 20h 3Fh 0Ah 0Dh 28h 03h 0Ah 00h FSCL(2) (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100kHz 1 MHz(1) 10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2: Actual frequency will depend on bus conditions. 2002 Microchip Technology Inc. Preliminary DS41159B-page 167 PIC18FXX8 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 17-18). FIGURE 17-18: SDA BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX DX-1 SCL allowed to transition high SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count. BRG Reload DS41159B-page 168 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.8 I2C MASTER MODE START CONDITION TIMING 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete. To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the START condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the SDA line held low and the START condition is complete. Note: If, at the beginning of the START condition, the SDA and SCL pins are already sampled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state. FIGURE 17-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of START bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit SDA TBRG 2nd bit Write to SEN bit occurs here TBRG SCL S TBRG 2002 Microchip Technology Inc. Preliminary DS41159B-page 169 PIC18FXX8 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). A Repeated START condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG, while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". 17.4.9.1 WCOL Status Flag If the user writes the SSPBUF when a Repeated START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated START condition is complete. FIGURE 17-20: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, SCL (no change) SDA = 1, SCL = 1 At completion of START bit, hardware clear RSEN bit and set SSPIF TBRG 1st bit SDA Falling edge of ninth clock End of Xmit Write to SSPBUF occurs here TBRG TBRG Sr = Repeated START TBRG TBRG SCL DS41159B-page 170 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.10 I2C MASTER MODE TRANSMISSION 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0), and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 17-21). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will de-assert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 17.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The RCEN bit should be set after ACK sequence is complete, or the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the baud rate generator is suspended from counting, holding SCL low. The MSSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). 17.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 17.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 17.4.11.3 WCOL Status Flag 17.4.10.1 BF Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software. 2002 Microchip Technology Inc. Preliminary DS41159B-page 171 FIGURE 17-21: DS41159B-page 172 Write SSPCON2<0> SEN = 1 START condition begins From slave clear ACKSTAT bit SSPCON2<6> R/W = 0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address D0 ACK SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 ACKSTAT in SSPCON2 = 1 SSPIF Cleared in software Cleared in software service routine From SSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SEN After START condition, SEN cleared by hardware SSPBUF is written in software PEN PIC18FXX8 I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Preliminary R/W 2002 Microchip Technology Inc. FIGURE 17-22: Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3>, (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically ACK RCEN = 1 start next receive RCEN cleared automatically ACK from Master SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here 2002 Microchip Technology Inc. A1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK is not sent Bus Master terminates transfer Write to SSPCON2<0> (SEN = 1) Begin START Condition SEN = 0 Write to SSPBUF occurs here Start XMIT Transmit Address to Slave SDA A7 A6 A5 A4 A3 A2 SCL S Set SSPIF interrupt at end of receive 1 5 1 2 3 4 5 1 2 3 4 2 3 4 8 6 7 8 9 6 7 9 5 6 7 8 9 Set SSPIF at end of receive P Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK SSPIF Cleared in software Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Preliminary SDA = 0, SCL = 1 while CPU responds to SSPIF Cleared in software Set P bit (SSPSTAT<4>) and SSPIF BF (SSPSTAT<0>) Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV SSPOV is set because SSPBUF is still full ACKEN PIC18FXX8 DS41159B-page 173 PIC18FXX8 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 STOP CONDITION TIMING A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the STOP sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 17-24). An Acknowledge sequence is enabled by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off and the MSSP module then goes into IDLE mode (Figure 17-23). 17.4.13.1 WCOL Status Flag 17.4.12.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Cleared in software Set SSPIF at the end of Acknowledge sequence Set SSPIF at the end of receive Note: TBRG = one baud rate generator period. Cleared in software DS41159B-page 174 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 Set PEN Falling edge of 9th clock TBRG SCL SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition. Note: TBRG = one baud rate generator period. 17.4.14 SLEEP OPERATION 17.4.17 While in SLEEP mode, the I2C module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled). MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION 17.4.15 EFFECT OF A RESET A RESET disables the MSSP module and terminates the current transfer. 17.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs. In multi-master operation, the SDA line must be monitored for arbitration, to see if the signal level is the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A START Condition A Repeated START Condition An Acknowledge Condition Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA, by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag BCLIF and reset the I2C port to its IDLE state (Figure 17-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is IDLE and the S and P bits are cleared. 2002 Microchip Technology Inc. Preliminary DS41159B-page 175 PIC18FXX8 FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master SDA Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred. SCL Set bus collision interrupt (BCLIF) BCLIF DS41159B-page 176 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.17.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and during this time, if the SCL pins are sampled as '0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a START condition is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address following the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START or STOP conditions. During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the START condition is aborted, * the BCLIF flag is set, and * the MSSP module is reset to its IDLE state (Figure 17-26). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START condition if SDA = 1, SCL=1 SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SEN cleared automatically because of bus collision. SSP module reset into IDLE state. BCLIF SSPIF SSPIF and BCLIF are cleared in software. 2002 Microchip Technology Inc. Preliminary DS41159B-page 177 PIC18FXX8 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. SEN BCLIF Interrupt cleared in software S SSPIF '0' '0' '0' '0' FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG TBRG Set SSPIF SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SEN BCLIF '0' S SSPIF SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software DS41159B-page 178 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 17.4.17.2 Bus Collision During a Repeated START Condition During a Repeated START condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data '1'. reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data '1' during the Repeated START condition, Figure 17-30. If, at the end of the BRG time-out both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated START condition is complete. When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then de-asserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data '0', Figure 17-29). If SDA is sampled high, the BRG is FIGURE 17-29: SDA BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software '0' '0' S SSPIF FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, Set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S SSPIF '0' 2002 Microchip Technology Inc. Preliminary DS41159B-page 179 PIC18FXX8 17.4.17.3 Bus Collision During a STOP Condition Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 17-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 17-32). b) FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, Set BCLIF SDA SDA asserted low SCL PEN BCLIF P SSPIF '0' '0' FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL PEN BCLIF P SSPIF '0' '0' SCL goes low before SDA goes high Set BCLIF DS41159B-page 180 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex). The SPEN (RCSTA register) and the TRISC<7> bits have to be set and the TRISC<6> bit must be cleared, in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. Register 18-1 shows the Transmit Status and Control Register (TXSTA) and Register 18-2 shows the Receive Status and Control Register (RCSTA). The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the three serial I/O modules incorporated into PIC18FXX8 devices. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, Serial EEPROMs, etc. REGISTER 18-1: TXSTA REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 bit 7 bit 6 bit 5 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4 bit 3 bit 2 bit 1 bit 0 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 181 PIC18FXX8 REGISTER 18-2: RCSTA REGISTER R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive (this bit is cleared after reception is complete.) Synchronous mode - Slave: Unused in this mode CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data Can be address/data bit or a parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 182 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 18.1 USART Baud Rate Generator (BRG) Example 18-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA register) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 18-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 18-1. From this, the error in baud rate can be determined. 18.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. EXAMPLE 18-1: Desired Baud Rate Solving for X: CALCULATING BAUD RATE ERROR = FOSC / (64 (X + 1)) X X X Calculated Baud Rate Error = ( (FOSC / Desired Baud Rate) / 64 ) - 1 = ((16000000 / 9600) / 64) - 1 = [25.042] = 25 = 16000000 / (64 (25 + 1)) = 9615 = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600) / 9600 = 0.16% TABLE 18-1: SYNC 0 1 BAUD RATE FORMULA BRGH = 0 (Low Speed) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) NA (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) Legend: X = value in SPBRG (0 to 255) TABLE 18-2: Name TXSTA RCSTA SPBRG REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on POR, BOR 0000 -010 0000 000x 0000 0000 Value on all other RESETS 0000 -010 0000 000x 0000 0000 Bit 7 CSRC SPEN Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG. 2002 Microchip Technology Inc. Preliminary DS41159B-page 183 PIC18FXX8 TABLE 18-3: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE SPBRG value (decimal) 129 103 32 19 0 255 SPBRG value (decimal) 207 51 41 12 7 0 255 SPBRG value (decimal) 103 51 12 9 2 1 0 255 33 MHz KBAUD NA NA NA NA NA 77.10 95.93 294.64 485.30 8250 32.23 10 MHz KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 % ERROR +0.16 -1.36 +0.16 +4.17 0 % ERROR +0.39 -0.07 -1.79 -2.94 SPBRG value (decimal) 106 85 27 16 0 255 SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 92 46 11 8 2 1 0 255 25 MHz KBAUD NA NA NA NA NA 77.16 96.15 297.62 480.77 6250 24.41 % ERROR +0.47 +0.16 -0.79 -3.85 SPBRG value (decimal) 80 64 20 12 0 255 SPBRG value (decimal) 185 92 22 18 5 3 0 255 SPBRG value (decimal) 207 103 25 12 2 2 0 0 255 20 MHz KBAUD NA NA NA NA NA 76.92 96.15 294.12 500 5000 19.53 % ERROR +0.16 +0.16 -1.96 0 SPBRG value (decimal) 64 51 16 9 0 255 SPBRG value (decimal) 131 65 16 12 3 2 0 255 SPBRG value (decimal) 26 6 2 0 0 255 FOSC = 40 MHz KBAUD NA NA NA NA NA 76.92 96.15 303.03 500 10000 39.06 % ERROR +0.16 +0.16 +1.01 0 - FOSC = 16 MHz KBAUD NA NA NA NA 19.23 76.92 95.24 307.70 500 4000 15.63 % ERROR +0.16 +0.16 -0.79 +2.56 0 - 7.15909 MHz KBAUD NA NA NA 9.62 19.24 77.82 94.20 298.35 447.44 1789.80 6.99 1 MHz KBAUD NA 1.20 2.40 9.62 19.23 83.33 83.33 250 NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 +8.51 -13.19 -16.67 % ERROR +0.23 +0.23 +1.32 -1.88 -0.57 -10.51 - 5.0688 MHz KBAUD NA NA NA 9.60 19.20 74.54 97.48 316.80 422.40 1267.20 4.95 % ERROR 0 0 -2.94 +1.54 +5.60 -15.52 - FOSC = 4 MHz KBAUD NA NA NA 9.62 19.23 76.92 1000 333.33 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 +11.11 0 - 3.579545 MHz KBAUD NA NA NA 9.62 19.04 74.57 99.43 298.30 447.44 894.89 3.50 % ERROR +0.23 -0.83 -2.90 +3.57 -0.57 -10.51 - 32.768 kHz KBAUD 0.30 1.17 2.73 8.20 NA NA NA NA NA 8.20 0.03 % ERROR +1.14 -2.48 +13.78 -14.67 - DS41159B-page 184 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 18-4: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) SPBRG value (decimal) 64 32 7 6 1 0 0 255 SPBRG value (decimal) 207 103 25 12 2 2 0 0 255 SPBRG value (decimal) 207 51 25 6 2 0 0 255 33 MHz KBAUD NA NA 2.40 9.55 19.10 73.66 103.13 257.81 NA 515.63 2.01 10 MHz KBAUD NA 1.20 2.40 9.77 19.53 78.13 78.13 156.25 NA 156.25 0.61 % ERROR +0.16 +0.16 +1.73 +1.73 +1.73 -18.62 -47.92 % ERROR -0.07 -0.54 -0.54 -4.09 +7.42 -14.06 SPBRG value (decimal) 214 53 26 6 4 1 0 255 SPBRG value (decimal) 129 64 15 7 1 1 0 0 255 SPBRG value (decimal) 185 46 22 5 2 0 0 255 25 MHz KBAUD NA NA 2.40 9.53 19.53 78.13 97.66 NA NA 390.63 1.53 % ERROR -0.15 -0.76 +1.73 +1.73 +1.73 SPBRG value (decimal) 162 40 19 4 3 0 255 SPBRG value (decimal) 92 46 11 5 0 0 255 SPBRG value (decimal) 51 12 6 1 0 0 255 20 MHz KBAUD NA NA 2.40 9.47 19.53 78.13 104.17 312.50 NA 312.50 1.22 % ERROR +0.16 -1.36 +1.73 +1.73 +8.51 +4.17 SPBRG value (decimal) 129 32 15 3 2 0 0 255 SPBRG value (decimal) 65 32 7 3 0 0 255 SPBRG value (decimal) 1 0 255 FOSC = 40 MHz KBAUD NA NA NA 9.62 18.94 78.13 89.29 312.50 625 625 2.44 % ERROR +0.16 -1.36 +1.73 -6.99 +4.17 +25.00 - FOSC = 16 MHz KBAUD NA 1.20 2.40 9.62 19.23 83.33 83.33 250 NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 +8.51 -13.19 -16.67 - 7.15909 MHz KBAUD NA 1.20 2.38 9.32 18.64 111.86 NA NA NA 111.86 0.44 1 MHz KBAUD 0.30 1.20 2.23 7.81 15.63 NA NA NA NA 15.63 0.06 % ERROR +0.16 +0.16 -6.99 -18.62 -18.62 % ERROR +0.23 -0.83 -2.90 -2.90 +45.65 - 5.0688 MHz KBAUD NA 1.20 2.40 9.90 19.80 79.20 NA NA NA 79.20 0.31 % ERROR 0 0 +3.13 +3.13 +3.13 - FOSC = 4 MHz KBAUD 0.30 1.20 2.40 8.93 20.83 62.50 NA NA NA 62.50 0.24 % ERROR -0.16 +1.67 +1.67 -6.99 +8.51 -18.62 - 3.579545 MHz KBAUD 0.30 1.19 2.43 9.32 18.64 55.93 NA NA NA 55.93 0.22 % ERROR +0.23 -0.83 +1.32 -2.90 -2.90 -27.17 - 32.768 kHz KBAUD 0.26 NA NA NA NA NA NA NA NA 0.51 0.002 % ERROR -14.67 - 2002 Microchip Technology Inc. Preliminary DS41159B-page 185 PIC18FXX8 TABLE 18-5: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 103 51 12 9 2 1 0 255 SPBRG value (decimal) 207 103 25 12 0 255 33 MHz KBAUD NA NA NA 9.60 19.28 76.39 98.21 294.64 515.63 2062.50 8,06 10 MHz KBAUD NA NA NA 9.62 18.94 78.13 89.29 312.50 625 625 2.44 % ERROR +0.16 -1.36 +1.73 -6.99 +4.17 +25.00 % ERROR -0.07 +0.39 -0.54 +2.31 -1.79 +3.13 SPBRG value (decimal) 214 106 26 20 6 3 0 255 SPBRG value (decimal) 64 32 7 6 1 0 0 255 SPBRG value (decimal) 185 92 22 11 2 1 0 0 255 25 MHz KBAUD NA NA NA 9.59 19.30 78.13 97.66 312.50 520.83 1562.50 6.10 % ERROR -0.15 +0.47 +1.73 +1.73 +4.17 +4.17 SPBRG value (decimal) 162 80 19 15 4 2 0 255 SPBRG value (decimal) 185 46 22 5 4 0 0 0 255 SPBRG value (decimal) 207 51 25 6 2 0 0 255 20 MHz KBAUD NA NA NA 9.62 19.23 78.13 96.15 312.50 416.67 1250 4.88 % ERROR +0.16 +0.16 +1.73 +0.16 +4.17 -16.67 SPBRG value (decimal) 129 64 15 12 3 2 0 255 SPBRG value (decimal) 131 32 16 3 2 0 0 255 SPBRG value (decimal) 6 1 0 0 255 FOSC = 40 MHz KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 % ERROR +0.16 -1.36 +0.16 +4.17 0 - FOSC = 16 MHz KBAUD NA NA NA 9.62 19.23 76.92 100 333.33 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 +11.11 0 - 7.15909 MHz KBAUD NA NA 2.41 9.52 19.45 74.57 89.49 447.44 447.44 447.44 1.75 1 MHz KBAUD 0.30 1.20 2.40 8.93 20.83 62.50 NA NA NA 62.50 0.24 % ERROR +0.16 +0.16 +0.16 -6.99 +8.51 -18.62 % ERROR +0.23 -0.83 +1.32 -2.90 -6.78 +49.15 -10.51 - 5.0688 MHz KBAUD NA NA 2.40 9.60 18.64 79.20 105.60 316.80 NA 316.80 1.24 % ERROR 0 0 -2.94 +3.13 +10.00 +5.60 - FOSC = 4 MHz KBAUD NA 1.20 2.40 9.62 19.23 NA NA NA NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 - 3.579545 MHz KBAUD NA 1.20 2.41 9.73 18.64 74.57 111.86 223.72 NA 55.93 0.22 % ERROR +0.23 +0.23 +1.32 -2.90 -2.90 +16.52 -25.43 - 32.768 kHz KBAUD 0.29 1.02 2.05 NA NA NA NA NA NA 2.05 0.008 % ERROR -2.48 -14.67 -14.67 - DS41159B-page 186 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 18.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits and one STOP bit). The most common data format is 8 bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH bit (TXSTA register). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing the SYNC bit (TXSTA register). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver. empty and flag bit TXIF (PIR registers) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA register) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. Steps to follow when setting up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 18.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). Note: TXIF is not cleared immediately upon loading data into the transmit buffer TXREG. The flag bit becomes valid in the second instruction cycle following the load instruction. 2. 3. 4. 5. 6. 7. 18.2.1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 18-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The TSR register obtains its data from the Read/Write Transmit Buffer register (TXREG). The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is FIGURE 18-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN *** TXIE LSb 0 Pin Buffer and Control RC6/TX/CK pin TSR register 2002 Microchip Technology Inc. Preliminary DS41159B-page 187 PIC18FXX8 FIGURE 18-2: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Register Empty Flag) Word 1 ASYNCHRONOUS TRANSMISSION START bit bit 0 bit 1 Word 1 bit 7/8 STOP bit TRMT bit (Transmit Shift Register Empty Flag) Word 1 Transmit Shift Reg FIGURE 18-3: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Word 1 Word 2 START bit bit 0 bit 1 Word 1 bit 7/8 STOP bit START bit Word 2 bit 0 TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 18-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 6 Bit 5 Bit 4 Bit 3 RBIE Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR Value on all other RESETS Bit 7 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE PIR1 PIE1 IPR1 RCSTA TXREG TXSTA PSPIF PSPIE PSPIP SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN SYNC TMR0IF INT0IF 0000 000x 0000 000u SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 ADDEN -- FERR BRGH OERR TRMT RX9D TX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 USART Transmit Register SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. DS41159B-page 188 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 18.2.2 USART ASYNCHRONOUS RECEIVER 18.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT The receiver block diagram is shown in Figure 18-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate, or at FOSC. This mode would typically be used in RS-232 systems. Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 18.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing enable bit CREN. This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is required, set the BRGH bit. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 2. 3. 4. 5. 6. 7. 8. 9. FIGURE 18-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN SPBRG / 64 or / 16 OERR FERR MSb STOP (8) 7 RSR Register *** LSb 0 START Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery 1 RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Data Bus Note: I/O pins have diode protection to VDD and VSS. 2002 Microchip Technology Inc. Preliminary DS41159B-page 189 PIC18FXX8 FIGURE 18-5: RX (pin) Rcv shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. ASYNCHRONOUS RECEPTION START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit Word 1 RCREG Word 2 RCREG TABLE 18-7: Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF CCP1IF Bit 1 INT0IF TMR2IF Bit 0 RBIF TMR1IF Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 TXEN BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 -010 0000 0000 GIE/GIEH PSPIF PSPIE PSPIP SPEN CSRC PEIE/GIEL TMR0IE ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN CCP1IE TMR2IE TMR1IE CCP1IP TMR2IP TMR1IP FERR OERR RX9D USART Receive Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. DS41159B-page 190 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 18.3 USART Synchronous Master Mode (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA register) shows the status of the TSR register. TRMT is a read only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Steps to follow when setting up a Synchronous Master Transmission: 1. Initialize the SPBRG register for the appropriate baud rate (Section 18.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. Note: TXIF is not cleared immediately upon loading data into the transmit buffer TXREG. The flag bit becomes valid in the second instruction cycle following the load instruction. In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA register). In addition, enable bit SPEN (RCSTA register) is set, in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA register). 18.3.1 USART SYNCHRONOUS MASTER TRANSMISSION 2. 3. 4. 5. 6. 7. The USART transmitter block diagram is shown in Figure 18-1. The heart of the transmitter is the Transmit (serial) Shift register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register (TXREG). The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and interrupt bit TXIF (PIR registers) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE TABLE 18-8: Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 -010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 -010 0000 0000 GIE/GIEH PSPIF PSPIE PSPIP SPEN CSRC USART Transmit Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. 2002 Microchip Technology Inc. Preliminary DS41159B-page 191 PIC18FXX8 FIGURE 18-6: SYNCHRONOUS TRANSMISSION Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit TRMT '1' Write Word 1 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 Write Word 2 TXEN bit '1' Note: Sync Master mode; SPBRG = '0'; continuous transmission of two 8-bit words. FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit0 bit1 bit2 bit6 bit7 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS41159B-page 192 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 18.3.2 USART SYNCHRONOUS MASTER RECEPTION Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 18.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. Once Synchronous Master mode is selected, reception is enabled by setting either enable bit SREN (RCSTA register), or enable bit CREN (RCSTA register). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. TABLE 18-9: Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 -010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE PSPIF PSPIE PSPIP SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN USART Receive Register Baud Rate Generator Register 0000 -010 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. FIGURE 18-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'. 2002 Microchip Technology Inc. Preliminary DS41159B-page 193 PIC18FXX8 18.4 USART Synchronous Slave Mode 18.4.2 Synchronous Slave mode differs from the Master mode, in that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA register). USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register, and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. Steps to follow when setting up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. 18.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. e) 6. Steps to follow when setting up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. 7. 8. 2. 3. 4. 5. 6. 7. DS41159B-page 194 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 GIE/GIEH PSPIF PSPIE PSPIP SPEN CSRC Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 -010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 -010 0000 0000 PEIE/GIEL TMR0IE ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN USART Transmit Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission. TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Bit 7 GIE/GIEH PSPIF PSPIE PSPIP SPEN CSRC Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR Value on all other RESETS 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 USART Receive Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. 2002 Microchip Technology Inc. Preliminary DS41159B-page 195 PIC18FXX8 NOTES: DS41159B-page 196 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.0 19.1 CAN MODULE Overview 19.1.1 OVERVIEW OF THE MODULE The Controller Area Network (CAN) module is a serial interface, useful for communicating with other peripherals or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The CAN module is a communication controller, implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is not covered within this data sheet. The reader may refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol CAN1.2, CAN2.0A and CAN2.0B * Standard and extended data frames * 0 - 8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Support for remote frames * Double-buffered receiver with two prioritized received message storage buffers * 6 full (standard/extended identifier) acceptance filters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer * 2 full acceptance filter masks, one each associated with the high and low priority receive buffers * Three transmit buffers with application specified prioritization and abort capability * Programmable wake-up functionality with integrated low pass filter * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to timer module for time-stamping and network synchronization * Low power SLEEP mode The CAN bus module consists of a protocol engine and message buffering and control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the 2 receive registers. The CAN Module supports the following frame types: * * * * * * Standard Data Frame Extended Data Frame Remote Frame Error Frame Overload Frame Reception Interframe Space CAN module uses RB3/CANRX and RB2/CANTX/INT2 pins to interface with CAN bus. In order to configure CANRX and CANTX as CAN interface: * bit TRISB<3> must be set; * bit TRISB<2> must be cleared. 19.1.2 TRANSMIT/RECEIVE BUFFERS The PIC18FXX8 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a total of six acceptance filters. Figure 19-1 is a block diagram of these buffers and their connection to the protocol engine. 2002 Microchip Technology Inc. Preliminary DS41159B-page 197 PIC18FXX8 FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Accept Acceptance Mask RXM1 Acceptance Filter RXM2 Accept Acceptance Mask RXM0 TXB1 MESSAGE Acceptance Filter RXF0 Acceptance Filter RXF1 TXB2 MESSAGE RXB0 Data and Identifier Data and Identifier RXB1 Acceptance Filter RXF3 Acceptance Filter RXF4 Acceptance Filter RXF5 BUFFERS TXREQ TXABT TXLARB TXERR TXBUFF TXREQ TXABT TXLARB TXERR TXBUFF TXREQ TXABT TXLARB TXERR TXBUFF TXB0 MESSAGE Message Request Message Queue Control Identifier Identifier Transmit Byte Sequencer Message Assembly Buffer PROTOCOL ENGINE Transmit Shift Receive Shift RXERRCNT Comparator CRC Register Bus-Off Bit Timing Generator Transmit Logic Protocol FSM Bit Timing Logic Transmit Error Counter Err-Pas Receive Error Counter TXERRCNT TX RX DS41159B-page 198 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.2 Note: CAN Module Registers Not all CAN registers are available in the access bank. 19.2.1 CAN CONTROL AND STATUS REGISTERS There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: * * * * * * Control and Status Registers Transmit Buffer Registers (Data and Control) Receive Buffer Registers (Data and Control) Baud Rate Control Registers I/O Control Register Interrupt Status and Control Registers The registers described in this section control the overall operation of the CAN module and show its operational status. REGISTER 19-1: CANCON - CAN CONTROL REGISTER R/W-1 REQOP2 bit 7 R/W-0 REQOP1 R/W-0 REQOP0 R/W-0 ABAT R/W-0 WIN2 R/W-0 WIN1 R/W-0 WIN0 U-0 -- bit 0 bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal WIN2:WIN0: Window Address bits This selects which of the CAN buffers to switch into the access bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE3:ICODE0 bits can be copied to the WIN3:WIN0 bits to select the correct buffer. See Example 19-1 for code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3-1 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 199 PIC18FXX8 REGISTER 19-2: CANSTAT - CAN STATUS REGISTER R-1 R-0 R-0 OPMODE2 OPMODE1 OPMODE0 bit 7 bit 7-5 U-0 -- R-0 ICODE2 R-0 ICODE1 R-0 ICODE0 U-0 -- bit 0 OPMODE2:OPMODE0: Operation Mode Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable mode 000 = Normal mode Note: Before the device goes into SLEEP mode, select Disable mode. bit 4 bit 3-1 Unimplemented: Read as '0' ICODE2:ICODE0: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in the ICODE3:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE3:ICODE0 bits can be copied to the WIN3:WIN0 bits to select the correct buffer to map into the Access Bank area. See Example 19-1 for code example. 111 = Wake-up on Interrupt 110 = RXB0 Interrupt 101 = RXB1 Interrupt 100 = TXB0 Interrupt 011 = TXB1 Interrupt 010 = TXB2 Interrupt 001 = Error Interrupt 000 = No Interrupt Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 DS41159B-page 200 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 EXAMPLE 19-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; ; ; ; ; Save CANSTAT register This is required to make sure that we use same CANSTAT value rather than one changed by another CAN interrupt. MOVF ANDLW ADDWF BRA BRA BRA BRA BRA BRA BRA TempCANSTAT, W b'00001110' PCL, F NoInterrupt ErrorInterrupt TXB2Interrupt TXB1Interrupt TXB0Interrupt RXB1Interrupt RXB0Interrupt ; Retrieve ICODE bits ; Perform computed GOTO ; to corresponding interrupt cause ; ; ; ; ; ; ; ; 000 001 010 011 100 101 110 111 = = = = = = = = No interrupt Error interrupt TXB2 interrupt TXB1 interrupt TXB0 interrupt RXB1 interrupt RXB0 interrupt Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here ... NoInterrupt ... ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. ; Clear the interrupt flag ; Handle error. ErrorInterrupt BCF PIR3, ERRIF ... RETFIE TXB2Interrupt BCF PIR3, TXB2IF GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF GOTO Accessbuffer ; Clear the interrupt flag ; Clear the interrupt flag ; Clear the interrupt flag ; Clear the interrupt flag 2002 Microchip Technology Inc. Preliminary DS41159B-page 201 PIC18FXX8 EXAMPLE 19-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ; Clear the interrupt flag RXB0Interrupt BCF PIR3, RXB0IF GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANCON.ICODE bits to CANSTAT.WIN bits MOVF TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW b'11110001' ; Use previously saved CANCON value to ; make sure same value. MOVWF TempCANCON ; Copy masked value back to TempCANCON MOVF ANDLW IORWF MOVFF TempCANSTAT, W b'00001110' TempCANCON TempCANCON, CANCON ; Retrieve ICODE bits ; Use previously saved CANSTAT value ; to make sure same value. ; Copy ICODE bits to WIN bits. ; Copy the result to actual CANCON ; Access current buffer... ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ANDLW b'11110001' IORWF TempCANCON ; Preserve current non WIN bits ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source DS41159B-page 202 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-3: COMSTAT - COMMUNICATION STATUS REGISTER R/C-0 R/C-0 RXB0OVFL RXB1OVFL bit 7 bit 7 R-0 TXBO R-0 TXBP R-0 RXBP R-0 R-0 TXWARN RXWARN R-0 EWARN bit 0 RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed TXBO: Transmitter Bus-Off bit 1 = Transmit Error Counter > 255 0 = Transmit Error Counter 255 TXBP: Transmitter Bus Passive bit 1 = Transmission Error Counter > 127 0 = Transmission Error Counter 127 RXBP: Receiver Bus Passive bit 1 = Receive Error Counter > 127 0 = Receive Error Counter 127 TXWARN: Transmitter Warning bit 1 = 127 Transmit Error Counter > 95 0 = Transmit Error Counter 95 RXWARN: Receiver Warning bit 1 = 127 Receive Error Counter > 95 0 = Receive Error Counter 95 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 203 PIC18FXX8 19.2.2 CAN TRANSMIT BUFFER REGISTERS This section describes the CAN Transmit Buffer registers and their associated control registers. REGISTER 19-4: TXBnCON - TRANSMIT BUFFER n CONTROL REGISTERS U-0 -- bit 7 R-0 TXABT R-0 TXLARB R-0 TXERR R/W-0 TXREQ U-0 -- R/W-0 TXPRI1 R/W-0 TXPRI0 bit 0 bit 7 bit 6 Unimplemented: Read as '0' TXABT: Transmission Aborted Status bit 1 = Message was aborted 0 = Message was not aborted TXLARB: Transmission Lost Arbitration Status bit 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERR: Transmission Error Detected Status bit 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQ: Transmit Request Status bit 1 = Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits. 0 = Automatically cleared when the message is successfully sent Note: Clearing this bit in software while the bit is set, will request a message abort. bit 5 bit 4 bit 3 bit 2 bit 1-0 Unimplemented: Read as '0' TXPRI1:TXPRI0: Transmit Priority bits 11 = Priority Level 3 (Highest Priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (Lowest Priority) Note: These bits set the order in which Transmit buffer will be transferred. They do not alter CAN message identifier. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 204 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER, HIGH BYTE R/W-x SID10 bit 7 bit 7-0 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 SID10:SID3: Standard Identifier bits, if EXIDE = 0 (TXBnSID Register) Extended Identifier bits EID28:EID21, if EXIDE = 1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-6: TXBnSIDL - TRANSMIT BUFFER n STANDARD IDENTIFIER, LOW BYTE R/W-x SID2 bit 7 R/W-x SID1 R/W-x SID0 R/W-x -- R/W-x EXIDE R/W-x -- R/W-x EID17 R/W-x EID16 bit 0 bit 7-5 bit 4 bit 3 SID2:SID0: Standard Identifier bits, if EXIDE = 0 Extended Identifier bits EID20:EID18, if EXIDE = 1 Unimplemented: Read as '0' EXIDE: Extended Identifier Enable bit 1 = Message will transmit Extended ID, SID10:SID0 becomes EID28:EID18 0 = Message will transmit Standard ID, EID17:EID0 are ignored Unimplemented: Read as '0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 2 bit 1-0 REGISTER 19-7: TXBnEIDH - TRANSMIT BUFFER n EXTENDED IDENTIFIER, HIGH BYTE R/W-x EID15 bit 7 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 205 PIC18FXX8 REGISTER 19-8: TXBnEIDL - TRANSMIT BUFFER n EXTENDED IDENTIFIER, LOW BYTE R/W-x EID7 bit 7 bit 7-0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-9: TXBnDm - TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 bit 7-0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0n<3 and 0 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-10: TXBnDLC - TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS U-0 -- bit 7 bit 7 bit 6 R/W-x TXRTR U-0 -- U-0 -- R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 Unimplemented: Read as '0' TXRTR: Transmission Frame Remote Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared Unimplemented: Read as '0' DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-4 bit 3-0 REGISTER 19-11: TXERRCNT - TRANSMIT ERROR COUNT REGISTER R-0 TEC7 bit 7 bit 7-0 R-0 TEC6 R-0 TEC5 R-0 TEC4 R-0 TEC3 R-0 TEC2 R-0 TEC1 R-0 TEC0 bit 0 TEC7:TEC0: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 207 PIC18FXX8 19.2.3 CAN RECEIVE BUFFER REGISTERS This section shows the Receive Buffer registers with their associated control registers. REGISTER 19-12: RXB0CON - RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 RXFUL(1) bit 7 bit 7 R/W-0 RXM1(1) R/W-0 RXM0(1) U-0 -- R-0 R/W-0 RXRTRRO RXB0DBEN R-0 JTOFF R/W-0 FILHIT0 bit 0 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and must be cleared by software after the buffer is read. bit 6-5 RXM1:RXM0: Receive Buffer Mode bits(1) 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages Unimplemented: Read as '0' RXRTRRO: Receive Remote Transfer Request Read Only bit 1 = Remote transfer request 0 = No remote transfer request RXB0DBEN: Receive Buffer 0 Double Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 JTOFF: Jump Table Offset bit (read only copy of RXB0DBEN) 1 = Allows Jump Table offset between 6 and 7 0 = Allows Jump Table offset between 1 and 0 Note: This bit allows same filter jump table for both RXB0CON and RXB1CON. bit 4 bit 3 bit 2 bit 1 bit 0 FILHIT0: Filter Hit bit This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Note Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 1: Bits RXFUL, RXM1 and RXM0 of RXB0CON are not mirrored in RXB1CON. DS41159B-page 208 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-13: RXB1CON - RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 RXFUL(1) bit 7 bit 7 R/W-0 RXM1(1) R/W-0 RXM0(1) U-0 -- R-0 RXRTRRO R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 bit 0 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read. bit 6-5 RXM1:RXM0: Receive Buffer Mode bits(1) 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages Unimplemented: Read as '0' RXRTRRO: Receive Remote Transfer Request bit (read only) 1 = Remote transfer request 0 = No remote transfer request FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0) only possible when RXB0DBEN bit is set Note Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 1: Bits RXFUL, RXM1 and RXM0 of RXB1CON are not mirrored in RXB0CON. bit 4 bit 3 bit 2-0 REGISTER 19-14: RXBnSIDH - RECEIVE BUFFER n STANDARD IDENTIFIER, HIGH BYTE REGISTER R/W-x SID10 bit 7 bit 7-0 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL Register) Extended Identifier bits EID28:EID21, if EXID = 1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 209 PIC18FXX8 REGISTER 19-15: RXBnSIDL - RECEIVE BUFFER n STANDARD IDENTIFIER, LOW BYTE R/W-x SID2 bit 7 bit 7-5 bit 4 R/W-x SID1 R/W-x SID0 R/W-x SRR R/W-x EXID U-0 -- R/W-x EID17 R/W-x EID16 bit 0 SID2:SID0: Standard Identifier bits, if EXID = 0 Extended Identifier bits EID20:EID18, if EXID = 1 SRR: Substitute Remote Request bit This bit is always `0' when EXID = `1', or equal to the value of RXRTRRO (RXnBCON<3>) when EXID = `0'. EXID: Extended Identifier bit 1 = Received message is an Extended Data Frame, SID10:SID0 are EID28:EID18 0 = Received message is a Standard Data Frame Unimplemented: Read as '0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 3 bit 2 bit 1-0 REGISTER 19-16: RXBnEIDH - RECEIVE BUFFER n EXTENDED IDENTIFIER, HIGH BYTE R/W-x EID15 bit 7 bit 7-0 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-17: RXBnEIDL - RECEIVE BUFFER n EXTENDED IDENTIFIER, LOW BYTE R/W-x EID7 bit 7 bit 7-0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 210 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-18: RXBnDLC - RECEIVE BUFFER n DATA LENGTH CODE REGISTERS U-0 -- bit 7 bit 7 bit 6 R/W-x RXRTR R/W-x RB1 R/W-x RB0 R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 Unimplemented: Read as '0' RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request RB1: Reserved bit 1 Reserved by CAN Spec and read as '0' RB0: Reserved bit 0 Reserved by CAN Spec and read as '0' DLC3:DLC0: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5 bit 4 bit 3-0 REGISTER 19-19: RXBnDm - RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 bit 7-0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0n<1 and 0 Preliminary DS41159B-page 211 PIC18FXX8 REGISTER 19-20: RXERRCNT - RECEIVE ERROR COUNT REGISTER R-0 REC7 bit 7 bit 7-0 R-0 REC6 R-0 REC5 R-0 REC4 R-0 REC3 R-0 REC2 R-0 REC1 R-0 REC0 bit 0 REC7:REC0: Receive Error Counter bits This register contains the Receive Error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not have the ability to put the module in "Bus-Off" state. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 19.2.3.1 Message Acceptance Filters and Masks This subsection describes the Message Acceptance filters and masks for the CAN Receive buffers. REGISTER 19-21: RXFnSIDH - RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER, HIGH BYTE R/W-x SID10 bit 7 bit 7-0 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0 Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-22: RXFnSIDL - RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER, LOW BYTE R/W-x SID2 bit 7 bit 7-5 bit 4 bit 3 R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDEN U-0 -- R/W-x EID17 R/W-x EID16 bit 0 SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0 Extended Identifier Filter bits EID20:EID18, if EXIDEN = 1 Unimplemented: Read as '0' EXIDEN: Extended Identifier Filter Enable bit 1 = Filter will only accept Extended ID messages 0 = Filter will only accept Standard ID messages Unimplemented: Read as '0' EID17:EID16: Extended Identifier Filter bits Legend: R = Readable bit - n = Value at POR bit 2 bit 1-0 W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. DS41159B-page 212 Preliminary PIC18FXX8 REGISTER 19-23: RXFnEIDH - RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER, HIGH BYTE R/W-x EID15 bit 7 bit 7-0 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 EID15:EID8: Extended Identifier Filter bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-24: RXFnEIDL - RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER, LOW BYTE R/W-x EID7 bit 7 bit 7-0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 EID7:EID0: Extended Identifier Filter bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-25: RXMnSIDH - RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK, HIGH BYTE R/W-x SID10 bit 7 bit 7-0 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 213 PIC18FXX8 REGISTER 19-26: RXMnSIDL - RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK, LOW BYTE R/W-x SID2 bit 7 bit 7-5 bit 4-2 bit 1-0 R/W-x SID1 R/W-x SID0 U-0 -- U-0 -- U-0 -- R/W-x EID17 R/W-x EID16 bit 0 SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18 Unimplemented: Read as '0' EID17:EID16: Extended Identifier Mask bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-27: RXMnEIDH - RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK, HIGH BYTE R/W-x EID15 bit 7 bit 7-0 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 EID15:EID8: Extended Identifier Mask bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 19-28: RXMnEIDL - RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK, LOW BYTE R/W-x EID7 bit 7 bit 7-0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 EID7:EID0: Extended Identifier Mask bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41159B-page 214 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.2.4 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers. REGISTER 19-29: BRGCON1 - BAUD RATE CONTROL REGISTER 1 R/W-0 SJW1 bit 7 bit 7-6 R/W-0 SJW0 R/W-0 BRP5 R/W-0 BRP4 R/W-0 BRP3 R/W-0 BRP2 R/W-0 BRP1 R/W-0 BRP0 bit 0 SJW1:SJW0: Synchronized Jump Width bits 11 = Synchronization Jump Width Time = 4 x TQ 10 = Synchronization Jump Width Time = 3 x TQ 01 = Synchronization Jump Width Time = 2 x TQ 00 = Synchronization Jump Width Time = 1 x TQ BRP5:BRP0: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-0 Note: This register is accessible in Configuration mode only. 2002 Microchip Technology Inc. Preliminary DS41159B-page 215 PIC18FXX8 REGISTER 19-30: BRGCON2 - BAUD RATE CONTROL REGISTER 2 R/W-0 SEG2PHTS bit 7 bit 7 R/W-0 SAM R/W-0 R/W-0 R/W-0 R/W-0 SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 R/W-0 PRSEG1 R/W-0 PRSEG0 bit 0 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point SEG1PH2:SEG1PH0: Phase Segment 1 bits 111 = Phase Segment 1 Time = 8 x TQ 110 = Phase Segment 1 Time = 7 x TQ 101 = Phase Segment 1 Time = 6 x TQ 100 = Phase Segment 1 Time = 5 x TQ 011 = Phase Segment 1 Time = 4 x TQ 010 = Phase Segment 1 Time = 3 x TQ 001 = Phase Segment 1 Time = 2 x TQ 000 = Phase Segment 1 Time = 1 x TQ PRSEG2:PRSEG0: Propagation Time Select bits 111 = Propagation Time = 8 x TQ 110 = Propagation Time = 7 x TQ 101 = Propagation Time = 6 x TQ 100 = Propagation Time = 5 x TQ 011 = Propagation Time = 4 x TQ 010 = Propagation Time = 3 x TQ 001 = Propagation Time = 2 x TQ 000 = Propagation Time = 1 x TQ Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5-3 bit 2-0 Note: This register is accessible in Configuration mode only. DS41159B-page 216 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-31: BRGCON3 - BAUD RATE CONTROL REGISTER 3 U-0 -- bit 7 bit 7 bit 6 R/W-0 WAKFIL U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 SEG2PH2(1) SEG2PH1(1) SEG2PH0(1) bit 0 Unimplemented: Read as '0' WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up Unimplemented: Read as '0' SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 Time = 8 x TQ 110 = Phase Segment 2 Time = 7 x TQ 101 = Phase Segment 2 Time = 6 x TQ 100 = Phase Segment 2 Time = 5 x TQ 011 = Phase Segment 2 Time = 4 x TQ 010 = Phase Segment 2 Time = 3 x TQ 001 = Phase Segment 2 Time = 2 x TQ 000 = Phase Segment 2 Time = 1 x TQ Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is clear. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-3 bit 2-0 19.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module's I/O pins in relation to the rest of the microcontroller. REGISTER 19-32: CIOCON - CAN I/O CONTROL REGISTER U-0 -- bit 7 bit 7-6 bit 5 U-0 -- R/W-0 ENDRHI R/W-0 CANCAP U-0 -- U-0 -- U-0 -- U-0 -- bit 0 Unimplemented: Read as `0' ENDRHI: Enable Drive High bit 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will tri-state when recessive CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture, RC2/CCP1 input to CCP1 module Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3-0 2002 Microchip Technology Inc. Preliminary DS41159B-page 217 PIC18FXX8 19.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 8.0. They are duplicated here for convenience. REGISTER 19-33: PIR3 - PERIPHERAL INTERRUPT FLAG REGISTER R/W-0 IRXIF bit 7 bit 7 R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXB2IF R/W-0 TXB1IF R/W-0 TXB0IF R/W-0 RXB1IF R/W-0 RXB0IF bit 0 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 218 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 19-34: PIE3 - PERIPHERAL INTERRUPT ENABLE REGISTER R/W-0 IRXIE bit 7 bit 7 R/W-0 WAKIE R/W-0 ERRIE R/W-0 TXB2IE R/W-0 TXB1IE R/W-0 TXB0IE R/W-0 RXB1IE R/W-0 RXB0IE bit 0 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 219 PIC18FXX8 REGISTER 19-35: IPR3 - PERIPHERAL INTERRUPT PRIORITY REGISTER R/W-1 IRXIP bit 7 bit 7 R/W-1 WAKIP R/W-1 ERRIP R/W-1 TXB2IP R/W-1 TXB1IP R/W-1 TXB0IP R/W-1 RXB1IP R/W-1 RXB0IP bit 0 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41159B-page 220 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 19-1: Address F7Fh CAN CONTROLLER REGISTER MAP Name -- Address F5Fh F5Eh F5Dh F5Ch F5Bh F5Ah F59h F58h F57h F56h F55h F54h F53h F52h F51h F50h F4Fh Name -- CANSTATRO1(2) RXB1D7 RXB1D6 RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON -- Address F3Fh F3Eh F3Dh F3Ch F3Bh F3Ah F39h F38h F37h F36h F35h F34h F33h F32h F31h F30h F2Fh Name -- CANSTATRO3(2) TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH TXB1SIDL TXB1SIDH TXB1CON -- Address F1Fh F1Eh F1Dh F1Ch F1Bh F1Ah F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h F0Fh F0Eh F0Dh F0Ch F0Bh F0Ah F09h F08h F07h F06h F05h F04h F03h F02h F01h F00h Name RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EIDL RXF5EIDH RXF5SIDL RXF5SIDH RXF4EIDL RXF4EIDH RXF4SIDL RXF4SIDH RXF3EIDL RXF3EIDH RXF3SIDL RXF3SIDH RXF2EIDL RXF2EIDH RXF2SIDL RXF2SIDH RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDL RXF0EIDH RXF0SIDL RXF0SIDH F7Eh -- F7Dh -- F7Ch -- F7Bh -- F7Ah -- F79h -- F78h -- F77h -- F76h TXERRCNT F75h RXERRCNT F74h COMSTAT F73h CIOCON F72h BRGCON3 F71h BRGCON2 F70h BRGCON1 F6Fh CANCON F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h CANSTAT RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON F4Eh CANSTATRO2(2) F4Dh TXB0D7 F4Ch TXB0D6 F4Bh TXB0D5 F4Ah TXB0D4 F49h TXB0D3 F48h TXB0D2 F47h TXB0D1 F46h TXB0D0 F45h TXB0DLC F44h TXB0EIDL F43h TXB0EIDH F42h TXB0SIDL F41h TXB0SIDH F40h TXB0CON F2Eh CANSTATRO4(2) F2Dh TXB2D7 F2Ch TXB2D6 F2Bh TXB2D5 F2Ah TXB2D4 F29h TXB2D3 F28h TXB2D2 F27h TXB2D1 F26h TXB2D0 F25h TXB2DLC F24h TXB2EIDL F23h TXB2EIDH F22h TXB2SIDL F21h TXB2SIDH F20h TXB2CON Note 1: Shaded registers are available in Access Bank Low area, while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register, due to the Microchip Header file requirement. 2002 Microchip Technology Inc. Preliminary DS41159B-page 221 PIC18FXX8 19.3 * * * * * * CAN Modes of Operation The PIC18FXX8 has six main modes of operation: Configuration mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes except Error Recognition are requested by setting the REQOP bits (CANCON<7:5>); Error Recognition is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is acknowledged by monitoring the OPMODE bits. When changing modes, the mode will not actually change until all pending message transmissions are complete. Because of this, the user must verify that the device has actually changed into the requested mode before further operations are executed. If REQOP<2:0> is set to `001', the module will enter the Module Disable mode. This mode is similar to disabling other peripheral modules by turning off the module enables. This causes the module internal clock to stop unless the module is active (i.e., receiving or transmitting a message). If the module is active, the module will wait for 11 recessive bits on the CAN bus, detect that condition as an idle bus, then accept the module disable command. OPMODE<2:0> = `001' indicates whether the module successfully went into Module Disable mode. The WAKIF interrupt is the only module interrupt that is still active in the Module Disable mode. If the WAKIE is set, the processor will receive an interrupt whenever the CAN bus detects a dominant state, as occurs with a SOF. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. 19.3.3 NORMAL MODE 19.3.1 CONFIGURATION MODE The CAN module has to be initialized before the activation. This is only possible if the module is in the Configuration mode. The Configuration mode is requested by setting REQOP2 bit. Only when the status bit OPMODE2 has a high level, can the initialization be performed. Afterwards, the configuration registers, the acceptance mask registers, and the acceptance filter registers can be written. The module is activated by setting the REQOP control bits to zero. The module will protect the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is on-line. The CAN module will not be allowed to enter the Configuration mode while a transmission is taking place. The CONFIG bit serves as a lock to protect the following registers. * * * * Configuration registers Bus Timing registers Identifier Acceptance Filter registers Identifier Acceptance Mask registers This is the standard operating mode of the PIC18FXX8. In this mode, the device actively monitors all bus messages and generates Acknowledge bits, error frames, etc. This is also the only mode in which the PIC18FXX8 will transmit messages over the CAN bus. 19.3.4 LISTEN ONLY MODE In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will have access to configuration registers that are access restricted in other modes. Listen Only mode provides a means for the PIC18FXX8 to receive all messages, including messages with errors. This mode can be used for bus monitor applications, or for detecting the baud rate in `hot plugging' situations. For auto-baud detection, it is necessary that there are at least two other nodes which are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received. The Listen Only mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or Acknowledge signals. The filters and masks can be used to allow only particular messages to be loaded into the receive registers, or the filter masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen Only mode is activated by setting the mode request bits in the CANCON register. 19.3.2 DISABLE MODE In Disable mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts will remain and the error counters will retain their value. DS41159B-page 222 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.3.5 LOOPBACK MODE 19.4.2 TRANSMIT PRIORITY This mode will allow internal transmission of messages from the transmit buffers to the receive buffers, without actually transmitting messages on the CAN bus. This mode can be used in system development and testing. In this mode, the ACK bit is ignored and the device will allow incoming messages from itself, just as if they were coming from another node. The Loopback mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or Acknowledge signals. The TXCAN pin will revert to port I/O while the device is in this mode. The filters and masks can be used to allow only particular messages to be loaded into the receive registers. The masks can be set to all zeros to provide a mode that accepts all messages. The Loopback mode is activated by setting the mode request bits in the CANCON register. Transmit priority is a prioritization within the PIC18FXX8 of the pending transmittable messages. This is independent from, and not related to, any prioritization implicit in the message arbitration scheme built into the CAN protocol. Prior to sending the SOF, the priority of all buffers that are queued for transmission is compared. The transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If TXP bits for a particular message buffer are set to 11, that buffer has the highest possible priority. If TXP bits for a particular message buffer are 00, that buffer has the lowest possible priority. FIGURE 19-2: TRANSMIT BUFFER BLOCK DIAGRAM TXREQ TXABT TXLARB TXERR TXBUFF TXREQ TXABT TXLARB TXERR TXBUFF TXB0 MESSAGE 19.3.6 ERROR RECOGNITION MODE The module can be set to ignore all errors and receive any message. The Error Recognition mode is activated by setting the RXM<1:0> bits in the RXBnCON registers to 11. In this mode, the data which is in the message assembly buffer until the error time, is copied in the receive buffer and can be read via the CPU interface. In addition, the data which was on the internal sampling of the CAN bus at the error time and the state vector of the protocol state machine and the bit counter CntCan, are stored in registers and can be read. TXB1 MESSAGE 19.4 19.4.1 CAN Message Transmission TRANSMIT BUFFERS Message Request The PIC18FXX8 implements three Transmit Buffers (Figure 19-2). Each of these buffers occupies 14 bytes of SRAM and are mapped into the device memory map. For the MCU to have write access to the message buffer, the TXREQ bit must be clear, indicating that the message buffer is clear of any pending message to be transmitted. At a minimum, the TXBnSIDH, TXBnSIDL, and TXBnDLC registers must be loaded. If data bytes are present in the message, the TXBnDm registers must also be loaded. If the message is to use extended identifiers, the TXBnEIDm registers must also be loaded and the EXIDE bit set. Prior to sending the message, the MCU must initialize the TXInE bit to enable or disable the generation of an interrupt when the message is sent. The MCU must also initialize the TXP priority bits (see Section 19.4.2). Message Queue Control TXREQ TXABT TXLARB TXERR TXBUFF TXB2 MESSAGE Transmit Byte Sequencer 2002 Microchip Technology Inc. Preliminary DS41159B-page 223 PIC18FXX8 19.4.3 INITIATING TRANSMISSION 19.4.4 ABORTING TRANSMISSION To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. Setting the TXREQ bit does not initiate a message transmission, it merely flags a message buffer as ready for transmission. Transmission will start when the device detects that the bus is available. The device will then begin transmission of the highest priority message that is ready. When the transmission has completed successfully, the TXREQ bit will be cleared, the TXBnIF bit will be set, and an interrupt will be generated if the TXBnIE bit is set. If the message transmission fails, the TXREQ will remain set, indicating that the message is still pending for transmission and one of the following condition flags will be set. If the message started to transmit but encountered an error condition, the TXERR and the IRXIF bits will be set and an interrupt will be generated. If the message lost arbitration, the TXLARB bit will be set. The MCU can request to abort a message by clearing the TXREQ bit associated with the corresponding message buffer (TXBnCON<3>). Setting the ABAT bit (CANCON<4>) will request an abort of all pending messages. If the message has not yet started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. The abort is indicated when the module sets the ABT bits for the corresponding buffer (TXBnCON<6>). If the message has started to transmit, it will attempt to transmit the current message fully. If the current message is transmitted fully and is not lost to arbitration or an error, the ABT bit will not be set, because the message was transmitted successfully. Likewise, if a message is being transmitted during an abort request and the message is lost to arbitration or an error, the message will not be retransmitted and the ABT bit will be set, indicating that the message was successfully aborted. DS41159B-page 224 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 19-3: TRANSMIT MESSAGE FLOW CHART Start The message transmission sequence begins when the device determines that the TXREQ for any of the transmit registers has been set. No Are any TXREQ bits = 1 ? Yes Clear: TXABT, TXLARB and TXERR Clearing the TXREQ bit while it is set, or setting the ABAT bit before the message has started transmission, will abort the message. No Is CAN bus Available to Start Transmission ? Yes Examine TXPRI <1:0> to Determine Highest Priority Message Is TXREQ = 0 ABAT = 1 ? Yes No Begin Transmission (SOF) Was Message Transmitted Successfully? Yes Set TXREQ = 0 No Set TXERR = 1 Is TXLARB = 1? Yes Generate Interrupt Is TXIE = 1? A message can also be aborted, if a message error or lost arbitration condition occurred during transmission. No Yes Arbitration Lost During Transmission No Set TXBUFE = 1 The TXIE bit determines if an interrupt should be generated when a message is successfully transmitted. Is TXREQ = 0 or TXABT = 1 ? No Yes Abort Transmission: Set TXABT = 1 END 2002 Microchip Technology Inc. Preliminary DS41159B-page 225 PIC18FXX8 19.5 19.5.1 Message Reception RECEIVE MESSAGE BUFFERING The PIC18FXX8 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB), which acts as a third receive buffer (see Figure 19-4). 19.5.2 RECEIVE BUFFERS Of the three receive buffers, the MAB is always committed to receiving the next message from the bus. The remaining two receive buffers are called RXB0 and RXB1 and can receive a complete message from the protocol engine. The MCU can access one buffer while the other buffer is available for message reception, or holding a previously received message. The MAB assembles all messages received. These messages will be transferred to the RXBn buffers, only if the acceptance filter criteria are met. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted. This means that, regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is overwritten with the MAB contents. Therefore, the contents of all registers in the buffer must be assumed to have been modified when any message is received. The RXM bits set special Receive modes. Normally, these bits are set to `00' to enable reception of all valid messages, as determined by the appropriate acceptance filters. In this case, the determination of whether or not to receive standard or extended messages is determined by the EXIDE bit in the acceptance filter register. If the RXM bits are set to `01' or `10', the receiver will accept only messages with standard or extended identifiers, respectively. If an acceptance filter has the EXIDE bit set, such that it does not correspond with the RXM mode, that acceptance filter is rendered useless. These two modes of RXM bits can be used in systems where it is known that only standard or extended messages will be on the bus. If the RXM bits are set to `11', the buffer will receive all messages, regardless of the values of the acceptance filters. Also, if a message has an error before the end of frame, that portion of the message assembled in the MAB before the error frame, will be loaded into the buffer. This mode has some value in debugging a CAN system and would not be used in an actual system environment. 19.5.4 TIME-STAMPING The CAN module can be programmed to generate a time-stamp for every message that is received. When enabled, the module generates a capture signal for CCP1, which in turns captures the value of either Timer1 or Timer3. This value can be used as the message time-stamp. To use the time-stamp capability, the CANCAP bit (CIOCAN<4>) must be set. This replaces the capture input for CCP1 with the signal generated from the CAN module. In addition, CCP1CON<3:0> must be set to `0011' to enable the CCP special event trigger for CAN events. When a message is moved into either of the receive buffers, the appropriate RXBnIF bit is set. This bit must be cleared by the MCU when it has completed processing the message in the buffer, in order to allow a new message to be received into the buffer. This bit provides a positive lockout to ensure that the MCU has finished with the message before the PIC18FXX8 attempts to load a new message into the receive buffer. If the RXBnIE bit is set, an interrupt will be generated to indicate that a valid message has been received. FIGURE 19-4: RECEIVE BUFFER BLOCK DIAGRAM Accept Acceptance Mask RXM1 Acceptance Filter RXM2 19.5.3 RECEIVE PRIORITY Accept Acceptance Mask RXM0 Acceptance Filter RXF0 Acceptance Filter RXF1 RXB0 is the higher priority buffer and has two message acceptance filters associated with it. RXB1 is the lower priority buffer and has four acceptance filters associated with it. The lower number of acceptance filters makes the match on RXB0 more restrictive and implies a higher priority for that buffer. Additionally, the RXB0CON register can be configured such that if RXB0 contains a valid message and another valid message is received, an overflow error will not occur and the new message will be moved into RXB1, regardless of the acceptance criteria of RXB1. There are also two programmable acceptance filter masks available, one for each receive buffer (see Section 4.5). When a message is received, bits <3:0> of the RXBnCON register will indicate the acceptance filter number that enabled reception and whether the received message is a remote transfer request. Acceptance Filter RXF3 Acceptance Filter RXF4 Acceptance Filter RXF5 RXB0 Identifier Data and Identifier Data and Identifier RXB1 Identifier Message Assembly Buffer DS41159B-page 226 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 19-5: MESSAGE RECEPTION FLOW CHART Start No Detect Start of Message? Yes Begin Loading Message into Message Assembly Buffer (MAB) Generate Error Frame No Valid Message Received? Yes Yes, meets criteria Yes, meets criteria Message for RXB1 for RXBO Identifier meets a Filter Criteria? No Go to Start The RXFUL bit determines if the receive register is empty and able to accept a new message. The RXB0DBEN bit determines if RXB0 can rollover into RXB1 if it is full. Is RXFUL = 0? Yes No Is RX0DBEN = 1? No Generate Overrun Error: Set RXB0OVFL Yes Move Message into RXB0 Generate Overrun Error: Set RXB1OVFL No Is RXFUL = 0? Set RXRDY = 1 No Yes Move Message into RXB1 Is ERRIE = 1? Yes Go to Start Set FILHIT <2:0> according to which Filter Criteria was met Set FILHIT <0> according to which Filter Criteria was met Set RXRDY = 1 Is RXIE = 1? Yes Generate Interrupt Yes Is RXIE = 1? No Set CANSTAT <3:0> according to which Receive Buffer the Message was loaded into No 2002 Microchip Technology Inc. Preliminary DS41159B-page 227 PIC18FXX8 19.6 Message Acceptance Filters and Masks For RXB1, the RXB1CON register contains the FILHIT<2:0> bits. They are coded as follows: * * * * * * 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 (RXF0) Note: 000 and 001 can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to rollover into RXB1. The Message Acceptance Filters and Masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers. Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values. If there is a match, that message will be loaded into the appropriate receive buffer. The filter masks are used to determine which bits in the identifier are examined with the filters. A truth table is shown below in Table 19-2 that indicates how each bit in the identifier is compared to the masks and filters to determine if a message should be loaded into a receive buffer. The mask, essentially determines which bits to apply the acceptance filters to. If any mask bit is set to a zero, then that bit will automatically be accepted, regardless of the filter bit. The coding of the RXB0DBEN bit enables these three bits to be used similarly to the FILHIT bits and to distinguish a hit on filter RXF0 and RXF1, in either RXB0, or after a rollover into RXB1. * * * * 111 = Acceptance Filter 1 (RXF1) 110 = Acceptance Filter 0 (RXF0) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 TABLE 19-2: Mask bit n 0 1 1 1 1 FILTER/MASK TRUTH TABLE Message Identifier bit n001 X 0 1 0 1 Accept or Reject bit n Accept Accept Reject Reject Accept Filter bit n X 0 0 1 1 If the RXB0DBEN bit is clear, there are six codes corresponding to the six filters. If the RXB0DBEN bit is set, there are six codes corresponding to the six filters, plus two additional codes corresponding to RXF0 and RXF1 filters that rollover into RXB1. If more than one acceptance filter matches, the FILHIT bits will encode the binary value of the lowest numbered filter that matched. In other words, if filter RXF2 and filter RXF4 match, FILHIT will be loaded with the value for RXF2. This essentially prioritizes the acceptance filters with a lower number filter having higher priority. Messages are compared to filters in ascending order of filter number. The mask and filter registers can only be modified when the PIC18FXX8 is in Configuration mode. The mask and filter registers cannot be read outside of Configuration mode. When outside of Configuration mode, all mask and filter registers will be read as `0'. Legend: X = don't care As shown in the Receive Buffers Block Diagram (Figure 19-4), acceptance filters RXF0 and RXF1, and filter mask RXM0 are associated with RXB0. Filters RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are associated with RXB1. When a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the FILHIT bit(s). FIGURE 19-6: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXMn0 RXFn1 RXMn1 RxRqst RXFn0 RXFnn RXMnn Message Assembly Buffer Identifier DS41159B-page 228 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.7 Baud Rate Setting The Nominal Bit Time is defined as TBIT = 1 / Nominal Bit rate The Nominal Bit Time can be thought of as being divided into separate, non-overlapping time segments. These segments (Figure 19-7) include: * * * * Synchronization Segment (Sync_Seg) Propagation Time Segment (Prop_Seg) Phase Buffer Segment 1 (Phase_Seg1) Phase Buffer Segment 2 (Phase_Seg2) All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding, which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitters clock. As oscillators and transmission time may vary from node to node; the receiver must have some type of Phase Lock Loop (PLL) synchronized to data transmission edges to synchronize and maintain the receiver clock. Since the data is NRZ coded, it is necessary to include bit stuffing to ensure that an edge occurs at least every six bit times, to maintain the Digital Phase Lock Loop (DPLL) synchronization. The bit timing of the PIC18FXX8 is implemented using a DPLL that is configured to synchronize to the incoming data, and provides the nominal timing for the transmitted data. The DPLL breaks each bit time into multiple segments, made up of minimal periods of time called the Time Quanta (TQ). Bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network transmission delay compensation, and sample point positioning, are defined by the programmable bit timing logic of the DPLL. All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same master oscillator clock frequency. For the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each segment. The Nominal Bit Rate is the number of bits transmitted per second, assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. The nominal bit rate is defined to be a maximum of 1 Mb/s. The time segments (and thus the Nominal Bit Time) are in turn made up of integer units of time called Time Quanta or TQ (see Figure 19-7). By definition, the nominal bit time is programmable from a minimum of 8 TQ to a maximum of 25 TQ. Also, by definition, the minimum Nominal Bit Time is 1 s, corresponding to a maximum 1 Mb/s rate. The actual duration is given by the relationship Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) The Time Quantum is a fixed unit derived from the oscillator period. It is also defined by the programmable baud rate prescaler with integer values from 1 to 64, in addition to a fixed divide-by-two for clock generation. Mathematically, this is TQ (s) = (2 * (BRP+1)) / FOSC (MHz) or TQ (s) = (2 * (BRP+1)) * TOSC (s) where FOSC is the clock frequency, TOSC is the corresponding oscillator period, and BRP is an integer (0 through 63) represented by the binary values of BRGCON1<5:0>. FIGURE 19-7: BIT TIME PARTITIONING Input Signal Sync Propagation Segment Segment Phase Segment 1 Phase Segment 2 Bit Time Intervals TQ Sample Point Nominal Bit Time 2002 Microchip Technology Inc. Preliminary DS41159B-page 229 PIC18FXX8 19.7.1 TIME QUANTA 19.7.3 PROPAGATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 19-2. This part of the bit time is used to compensate for physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The length of the Propagation Segment can be programmed from 1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits. EXAMPLE 19-2: CALCULATING TQ, NOMINAL BIT RATE AND NOMINAL BIT TIME 19.7.4 PHASE BUFFER SEGMENTS TQ (s) = (2 * (BRP+1)) / FOSC (MHz) TBIT (s) = TQ (s) * number of TQ per bit interval Nominal Bit Rate (bits/s) = 1 / TBIT CASE 1: For FOSC = 16 MHz, BRP<5:0> = 00h, and Nominal Bit Time = 8 TQ: TQ = (2*1) / 16 = 0.125 s (125 ns) TBIT = 8 * 0.125 = 1 s (10-6 s) Nominal Bit Rate = 1 / 10-6 = 106 bits/s (1 Mb/s) CASE 2: For FOSC = 20 MHz, BRP<5:0> = 01h, and Nominal Bit Time = 8 TQ: TQ = (2*2) / 20 = 0.2 s (200 ns) TBIT = 8 * 0.2 = 1.6 s (1.6 * 10-6 S) Nominal Bit Rate = 1 / 1.6 * 10-6 s = 625,000 bits/s (625 Kb/s) CASE 3: For FOSC = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit Time = 25 TQ: TQ = (2*64) / 25 = 5.12 s TBIT = 25 * 5.12 = 128 s (1.28 * 10-4 s) Nominal Bit Rate = 1 / 1.28 * 10 = 7813 bits/s (7.8 Kb/s) The frequencies of the oscillators in the different nodes must be coordinated in order to provide a system wide specified nominal bit time. This means that all oscillators must have a TOSC that is an integral divisor of TQ. It should also be noted that although the number of TQ is programmable from 4 to 25, the usable minimum is 8 TQ. A bit time of less than 8 TQ in length is not guaranteed to operate correctly. -4 The Phase Buffer Segments are used to optimally locate the sampling point of the received bit, within the nominal bit time. The sampling point occurs between phase segment 1 and phase segment 2. These segments can be lengthened or shortened by the resynchronization process. The end of phase segment 1 determines the sampling point within a bit time. Phase segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase segment 2 provides delay before the next transmitted data transition and is also programmable from 1 TQ to 8 TQ in duration. However, due to IPT requirements, the actual minimum length of phase segment 2 is 2 TQ, or it may be defined to be equal to the greater of phase segment 1 or the Information Processing Time (IPT). 19.7.5 SAMPLE POINT The Sample Point is the point of time at which the bus level is read and the value of the received bit is determined. The sampling point occurs at the end of phase segment 1. If the bit timing is slow and contains many TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is determined to be the value of the majority decision of three values. The three samples are taken at the sample point, and twice before, with a time of TQ/2 between each sample. 19.7.6 INFORMATION PROCESSING TIME The Information Processing Time (IPT) is the time segment, starting at the sample point that is reserved for calculation of the subsequent bit level. The CAN specification defines this time to be less than or equal to 2 TQ. The PIC18FXX8 defines this time to be 2 TQ. Thus, phase segment 2 must be at least 2 TQ long. 19.7.2 SYNCHRONIZATION SEGMENT This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. DS41159B-page 230 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.8 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync Seg). The circuit will then adjust the values of phase segment 1 and phase segment 2, as necessary. There are two mechanisms used for synchronization. The phase error of an edge is given by the position of the edge relative to Sync Seg, measured in TQ. The phase error is defined in magnitude of TQ as follows: * e = 0 if the edge lies within SYNCESEG. * e > 0 if the edge lies before the SAMPLE POINT. * e < 0 if the edge lies after the SAMPLE POINT of the previous bit If the magnitude of the phase error is less than, or equal to, the programmed value of the synchronization jump width, the effect of a resynchronization is the same as that of a hard synchronization. If the magnitude of the phase error is larger than the synchronization jump width, and if the phase error is positive, then phase segment 1 is lengthened by an amount equal to the synchronization jump width. If the magnitude of the phase error is larger than the resynchronization jump width, and if the phase error is negative, then phase segment 2 is shortened by an amount equal to the synchronization jump width. 19.8.1 HARD SYNCHRONIZATION Hard synchronization is only done when there is a recessive to dominant edge during a BUS IDLE condition, indicating the start of a message. After hard synchronization, the bit time counters are restarted with Sync Seg. Hard synchronization forces the edge which has occurred to lie within the synchronization segment of the restarted bit time. Due to the rules of synchronization, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 19.8.3 SYNCHRONIZATION RULES 19.8.2 RESYNCHRONIZATION As a result of resynchronization, phase segment 1 may be lengthened, or phase segment 2 may be shortened. The amount of lengthening or shortening of the phase buffer segments has an upper bound given by the Synchronization Jump Width (SJW). The value of the SJW will be added to phase segment 1 (see Figure 19-8), or subtracted from phase segment 2 (see Figure 19-9). The SJW is programmable between 1 TQ and 4 TQ. Clocking information will only be derived from recessive to dominant transitions. The property, that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. * Only one synchronization within one bit time is allowed. * An edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge. * All other recessive to dominant edges fulfilling rules 1 and 2, will be used for resynchronization, with the exception that a node transmitting a dominant bit will not perform a resynchronization as a result of a recessive to dominant edge with a positive phase error. FIGURE 19-8: Input Signal Bit Time Segments TQ Sync LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Prop Segment Phase Segment 1 SJW Phase Segment 2 Sample Point Nominal Bit Length Actual Bit Length 2002 Microchip Technology Inc. Preliminary DS41159B-page 231 PIC18FXX8 FIGURE 19-9: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Sync Prop Segment Phase Segment 1 Phase Segment 2 SJW TQ Actual Bit Length Sample Point Nominal Bit Length 19.9 Programming Time Segments 19.11.1 BRGCON1 Some requirements for programming of the time segments: * Prop Seg + Phase Seg 1 Phase Seg 2 * Phase Seg 2 Sync Jump Width. For example, assume that a 125 kHz CAN baud rate is desired, using 20 MHz for FOSC. With a TOSC of 50 ns, a baud rate prescaler value of 04h gives a TQ of 500 ns. To obtain a Nominal Bit Rate of 125 kHz, the Nominal Bit Time must be 8 s, or 16 TQ. Using 1 TQ for the Sync Segment, 2 TQ for the Propagation Segment and 7 TQ for Phase Segment 1 would place the sample point at 10 TQ after the transition. This leaves 6 TQ for Phase Segment 2. By the rules above, the Sync Jump Width could be the maximum of 4 TQ. However, normally a large SJW is only necessary when the clock generation of the different nodes is inaccurate or unstable, such as using ceramic resonators. Typically, an SJW of 1 is enough. The BRP bits control the baud rate prescaler. The SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. 19.11.2 BRGCON2 19.10 Oscillator Tolerance As a rule of thumb, the bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 Kbit/sec. For the full bus speed range of the CAN protocol, a quartz oscillator is required. A maximum node-to-node oscillator variation of 1.7% is allowed. The PRSEG bits set the length of the propagation segment in terms of TQ. The SEG1PH bits set the length of phase segment 1 in TQ. The SAM bit controls how many times the RXCAN pin is sampled. Setting this bit to a `1' causes the bus to be sampled three times; twice at TQ/2 before the sample point, and once at the normal sample point (which is at the end of phase segment 1). The value of the bus is determined to be the value read during at least two of the samples. If the SAM bit is set to a `0', then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the length of phase segment 2 is determined. If this bit is set to a `1', then the length of phase segment 2 is determined by the SEG2PH bits of BRGCON3. If the SEG2PHTS bit is set to a `0', then the length of phase segment 2 is the greater of phase segment 1 and the information processing time (which is fixed at 2 TQ for the PIC18FXX8). 19.11.3 BRGCON3 19.11 Bit Timing Configuration Registers The configuration registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18FXX8 is in Configuration mode. The PHSEG2<2:0> bits set the length (in TQ) of phase segment 2, if the SEG2PHTS bit is set to a `1'. If the SEG2PHTS bit is set to a `0', then the PHSEG2<2:0> bits have no effect. DS41159B-page 232 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 19.12 Error Detection The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. 19.12.6 ERROR STATES 19.12.1 CRC ERROR With the Cyclic Redundancy Check (CRC), the transmitter calculates special check bits for the bit sequence, from the start of a frame until the end of the data field. This CRC sequence is transmitted in the CRC field. The receiving node also calculates the CRC sequence using the same formula and performs a comparison to the received sequence. If a mismatch is detected, a CRC error has occurred and an error frame is generated. The message is repeated. 19.12.2 ACKNOWLEDGE ERROR Detected errors are made public to all other nodes via error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each CAN node is in one of the three error states "error-active", "error-passive" or "busoff" according to the value of the internal error counters. The error-active state is the usual state, where the bus node can transmit messages and activate error frames (made of dominant bits), without any restrictions. In the error-passive state, messages and passive error frames (made of recessive bits) may be transmitted. The bus-off state makes it temporarily impossible for the station to participate in the bus communication. During this state, messages can neither be received nor transmitted. In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which was sent out as a recessive bit) contains a dominant bit. If not, no other node has received the frame correctly. An Acknowledge Error has occurred; an error frame is generated and the message will have to be repeated. 19.12.7 ERROR MODES AND ERROR COUNTERS 19.12.3 FORM ERROR The PIC18FXX8 contains two error counters: the Receive Error Counter (RXERRCNT), and the Transmit Error Counter (TXERRCNT). The values of both counters can be read by the MCU. These counters are incremented or decremented in accordance with the CAN bus specification. The PIC18FXX8 is error-active if both error counters are below the error-passive limit of 128. It is errorpassive if at least one of the error counters equals or exceeds 128. It goes to bus-off if the transmit error counter equals or exceeds the bus-off limit of 256. The device remains in this state until the bus-off recovery sequence is received. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure 19-10). Note that the CAN module, after going bus-off, will recover back to error-active without any intervention by the MCU, if the bus remains IDLE for 128 X 11 bit times. If this is not desired, the error Interrupt Service Routine should address this. The current Error mode of the CAN module can be read by the MCU via the COMSTAT register. Additionally, there is an error state warning flag bit, EWARN, which is set if at least one of the error counters equals or exceeds the error warning limit of 96. EWARN is reset if both error counters are less than the error warning limit. lf a node detects a dominant bit in one of the four segments, including end of frame, interframe space, Acknowledge delimiter, or CRC delimiter, then a Form Error has occurred and an error frame is generated. The message is repeated. 19.12.4 BIT ERROR A Bit Error occurs if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual bus level and comparing it to the just transmitted bit. In the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the Acknowledge slot, no bit error is generated because normal arbitration is occurring. 19.12.5 STUFF BIT ERROR lf, between the start of frame and the CRC delimiter, six consecutive bits with the same polarity are detected, the bit stuffing rule has been violated. A Stuff Bit Error occurs and an error frame is generated. The message is repeated. 2002 Microchip Technology Inc. Preliminary DS41159B-page 233 PIC18FXX8 FIGURE 19-10: ERROR MODES STATE DIAGRAM RESET RXERRCNT < 127 or TXERRCNT < 127 ErrorActive 128 occurrences of 11 consecutive "recessive" bits RXERRCNT > 127 or TXERRCNT > 127 ErrorPassive TXERRCNT > 255 BusOff 19.13 CAN Interrupts The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The CANINTF register contains interrupt flags. The CANINTE register contains the enables for the 8 main interrupts. A special set of read only bits in the CANSTAT register, the ICODE bits, can be used in combination with a jump table for efficient handling of interrupts. All interrupts have one source, with the exception of the Error Interrupt. Any of the Error Interrupt sources can set the Error Interrupt Flag. The source of the Error Interrupt can be determined by reading the Communication Status register, COMSTAT. The interrupts can be broken up into two categories: receive and transmit interrupts. The receive related interrupts are: * * * * * * * * * Receive Interrupts Wake-up Interrupt Receiver Overrun Interrupt Receiver Warning Interrupt Receiver Error-Passive Interrupt Transmit Interrupts Transmitter Warning Interrupt Transmitter Error-Passive Interrupt Bus-Off Interrupt 19.13.1 INTERRUPT CODE BITS The source of a pending interrupt is indicated in the ICODE (interrupt code) bits of the CANSTAT register (ICOD<2:0>). Interrupts are internally prioritized such that the higher priority interrupts are assigned lower ICODE values. Once the highest priority interrupt condition has been cleared, the code for the next highest priority interrupt that is pending (if any), will be reflected by the ICODE bits (see Table 19-3, following page). Note that only those interrupt sources that have their associated CANINTE enable bit set will be reflected in the ICODE bits. 19.13.2 TRANSMIT INTERRUPT When the Transmit Interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. The TXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU resetting the TXBnIF bit to a `0'. 19.13.3 RECEIVE INTERRUPT The transmit related interrupts are: When the Receive Interrupt is enabled, an interrupt will be generated when a message has been successfully received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving the EOF field. The RXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU resetting the RXBnIF bit to a `0'. DS41159B-page 234 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 19-3: ICOD <2:0> 000 001 010 011 100 101 110 111 VALUES FOR ICODE<2:0> Boolean Expression ERR*WAK*TX0*TX1*TX2*RX0* RX1 ERR ERR*TX0*TX1*TX2 ERR*TX0*TX1 ERR*TX0 ERR*TX0*TX1*TX2*RX0*RX1 ERR*TX0*TX1*TX2*RX0 ERR*TX0*TX1*TX2*RX0*RX1* WAK 19.13.6 ERROR INTERRUPT Interrupt None Error TXB2 TXB1 TXB0 RXB1 RXB0 Wake on Interrupt When the Error Interrupt is enabled, an interrupt is generated if an overflow condition occurs, or if the error state of transmitter or receiver has changed. The error flags in COMSTAT will indicate one of the following conditions. 19.13.6.1 Receiver Overflow An overflow condition occurs when the MAB has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated COMSTAT.RXnOVFL bit will be set to indicate the overflow condition. This bit must be cleared by the MCU. 19.13.6.2 Receiver Warning The receive error counter has reached the MCU warning limit of 96. Key: ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE TX2 = TXB2IF * TXB2IE 19.13.6.3 Transmitter Warning The transmit error counter has reached the MCU warning limit of 96. 19.13.6.4 19.13.4 MESSAGE ERROR INTERRUPT Receiver Bus Passive When an error occurs during transmission or reception of a message, the message error flag IRXIF will be set and if the IRXIE bit is set, an interrupt will be generated. This is intended to be used to facilitate baud rate determination when used in conjunction with Listen Only mode. The receive error counter has exceeded the errorpassive limit of 127 and the device has gone to error-passive state. 19.13.6.5 Transmitter Bus Passive The transmit error counter has exceeded the errorpassive limit of 127 and the device has gone to error- passive state. 19.13.5 BUS ACTIVITY WAKE-UP INTERRUPT 19.13.6.6 Bus-Off When the PIC18FXX8 is in SLEEP mode and the Bus Activity Wake-up Interrupt is enabled, an interrupt will be generated, and the WAKIF bit will be set when activity is detected on the CAN bus. This interrupt causes the PIC18FXX8 to exit SLEEP mode. The interrupt is reset by the MCU, clearing the WAKIF bit. The transmit error counter has exceeded 255 and the device has gone to bus-off state. 19.13.7 INTERRUPT ACKNOWLEDGE Interrupts are directly associated with one or more status flags in the PIR register. Interrupts are pending as long as one of the flags is set. Once an interrupt flag is set by the device, the flag can not be reset by the microcontroller until the interrupt condition is removed. 2002 Microchip Technology Inc. Preliminary DS41159B-page 235 PIC18FXX8 NOTES: DS41159B-page 236 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 20.0 COMPATIBLE 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) The Analog-to-Digital (A/D) Converter module has five inputs for the PIC18F2X8 devices and eight for the PIC18F4X8 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible with the PICmicro(R) mid-range A/D module. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. The ADCON0 register, shown in Register 20-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 20-2, configures the functions of the port pins. REGISTER 20-1: ADCON0 REGISTER R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold) ADCON1 0 0 0 0 1 1 1 1 ADCON0 00 01 10 11 00 01 10 11 Clock Conversion FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = channel 0 (AN0) 001 = channel 1 (AN1) 010 = channel 2 (AN2) 011 = channel 3 (AN3) 100 = channel 4 (AN4) 101 = channel 5 (AN5)(1) 110 = channel 6 (AN6)(1) 111 = channel 7 (AN7)(1) Note 1: These channels are unimplemented on PIC18CF2X8 (28-pin) devices. Do not select any unimplemented channel. bit 2 bit 1 bit 0 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 237 PIC18FXX8 REGISTER 20-2: ADCON1 REGISTER R/W-0 ADFM bit 7 bit 7 R/W-0 ADCS2 U-0 -- U-0 -- R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 ADFM: A/D Result Format Select bit. 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as '0'. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as '0'. ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold) ADCON1 ADCON0 bit 6 bit 5-4 bit 3-0 Unimplemented: Read as '0' PCFG3:PCFG0: A/D Port Configuration Control bits PCFG 0000 0001 0010 0011 0100 0101 011x 1000 1001 1010 1011 1100 1101 1110 1111 AN7 A A D D D D D A D D D D D D D AN6 A A D D D D D A D D D D D D D AN5 A A D D D D D A A A A D D D D AN4 A A A A D D D A A A A A D D D AN3 A VREF+ A VREF+ A VREF+ D VREF+ A VREF+ VREF+ VREF+ VREF+ D VREF+ AN2 A A A A D D D VREFA A VREFVREFVREFD VREF- AN1 A A A A A A D A A A A A A D D AN0 A A A A A A D A A A A A A A A VREF+ VDD AN3 VDD AN3 VDD AN3 -- AN3 VDD AN3 AN3 AN3 AN3 VDD AN3 VREFVSS VSS VSS VSS VSS VSS -- AN2 VSS VSS AN2 AN2 AN2 VSS AN2 C/R 8/0 7/1 5/0 4/1 3/0 2/1 0/0 6/2 6/0 5/1 4/2 3/2 2/2 1/0 1/2 A = Analog input D = Digital I/O C / R = # of analog input channels / # of A/D voltage references Note: Legend: R = Readable bit - n = Value at POR reset Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown Shaded cells indicate channels available only on PIC18F4X8 devices. On any device RESET, the port pins that are multiplexed with analog functions (ANx) are forced to be analog inputs. DS41159B-page 238 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/VREF+ pin and RA2/AN2/VREF- pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference), or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 20-1. FIGURE 20-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 110 101 100 VAIN (Input Voltage) 10-bit Converter A/D PCFG0 VDD VREF+ Reference voltage VREF011 010 001 000 AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 VSS Note 1: Channels AN5 through AN7 are not available on PIC18F2X8 devices. 2: All I/O pins have diode protection to VDD and VSS. 2002 Microchip Technology Inc. Preliminary DS41159B-page 239 PIC18FXX8 The value that is in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt 6. 7. Read A/D Result registers (ADRESH/ADRESL); clear bit ADIF if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts. 20.1 A/D Acquisition Requirements 2. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. 3. 4. 5. FIGURE 20-2: ANALOG INPUT MODEL VDD VT = 0.6V Sampling Switch RIC 1k SS RSS Rs ANx VAIN CPIN 5 pF VT = 0.6V I LEAKAGE 500 nA CHOLD = 120 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k) DS41159B-page 240 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 20-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: * * * * * * CHOLD Rs Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0 EQUATION 20-1: TACQ = = ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF EQUATION 20-2: VHOLD or Tc = = A/D MINIMUM CHARGING TIME (VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) -(120 pF)(1 k + RSS + RS) ln(1/2047) EXAMPLE 20-1: TACQ TACQ TC = = = CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TAMP + TC + TCOFF 2 s + TC + [(Temp - 25C)(0.05 s/C)] -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004885) -120 pF (10.5 k) ln(0.0004885) -1.26 s (-7.6241) 9.61 s 2 s + 9.61 s + [(50C - 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s Temperature coefficient is only required for temperatures > 25C. TACQ = 2002 Microchip Technology Inc. Preliminary DS41159B-page 241 PIC18FXX8 20.2 Selecting the A/D Conversion Clock 20.3 Configuring Analog Port Pins The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC oscillator. The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may cause the input buffer to consume current that is out of the devices specification. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 20-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 20-1: Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC Legend: Note 1: 2: 3: TAD vs. DEVICE OPERATING FREQUENCIES Device Frequency 20 MHz 100 ns(2) 200 ns(2) 400 ns(2) 800 ns(2) 1.6 s 3.2 s 2 - 6 s(1) 5 MHz 400 ns(2) 800 ns(2) 1.6 s 3.2 s 6.4 s 12.8 s 2 - 6 s(1) 1.25 MHz 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s(3) 51.2 s(3) 2 - 6 s(1) 333.33 kHz 6 s 12 s 24 s(3) 48 s(3) 96 s(3) 192 s(3) 2 - 6 s(1) ADCS2:ADCS0 000 100 001 101 010 110 011 AD Clock Source (TAD) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. TABLE 20-2: Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC Legend: Note 1: 2: 3: TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LC DEVICES) Device Frequency 4 MHz 500 ns(2) 1.0 s(2) 2.0 s(2) 4.0 s(2) 8.0 s 16.0 s 3 - 9 s(1,4) 2 MHz 1.0 s(2) 2.0 s(2) 4.0 s 8.0 s 16.0 s 32.0 s 3 - 9 s(1,4) 1.25 MHz 1.6 s(2) 3.2 s(2) 6.4 s 12.8 s 25.6 s(3) 51.2 s(3) 3 - 9 s(1,4) 333.33 kHz 6 s 12 s 24 s(3) 48 s(3) 96 s(3) 192 s(3) 3 - 9 s(1,4) ADCS2:ADCS0 000 100 001 101 010 110 011 AD Clock Source (TAD) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 6 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. DS41159B-page 242 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 20.4 A/D Conversions 20.5 Use of the ECCP Trigger Figure 20-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. An A/D conversion can be started by the "special event trigger" of the ECCP module. This requires that the ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. FIGURE 20-3: A/D CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. TABLE 20-3: Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 PORTA TRISA PORTE LATE TRISE Bit 7 SUMMARY OF A/D REGISTERS Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- Bit 4 INT0IE TXIF TXIE TXIP EEIF EEIE EEIP Bit 3 RBIE SSPIF SSPIE SSPIP BCLIF BCLIE BCLIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) -- -- -- ADIF ADIE ADIP CMIF(1) CMIE(1) CMIP(1) 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ECCP1IF(1) -0-0 0000 -0-0 0000 TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000 TMR3IP ECCP1IP(1) -0-0 0000 -0-0 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu A/D Result Register A/D Result Register ADCS1 ADFM -- -- -- -- IBF ADCS0 ADCS2 RA6 -- -- OBF CHS2 -- RA5 -- -- IBOV CHS1 -- RA4 -- -- PSPMODE CHS0 PCFG3 RA3 -- -- GO/DONE PCFG2 RA2 RE2 LATE2 TRISE2 -- PCFG1 RA1 RE1 LATE1 TRISE1 ADON PCFG0 RA0 RE0 LATE0 TRISE0 0000 00-0 0000 00-0 00-- 0000 00-- 0000 -00x 0000 -00u 0000 -111 1111 -111 1111 ---- -000 ---- -000 ---- -xxx ---- -uuu 0000 -111 0000 -111 PORTA Data Direction Register -- Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear. 2002 Microchip Technology Inc. Preliminary DS41159B-page 243 PIC18FXX8 NOTES: DS41159B-page 244 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 21.0 Note: COMPARATOR MODULE The analog comparators are only available on the PIC18F448 and PIC18F458. The CMCON register, shown in Register 21-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 21-1. The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RD0 through RD3 pins. The On-Chip Voltage Reference (Section 22.0) can also be an input to the comparators. REGISTER 21-1: CMCON REGISTER R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RD0/PSP0 C2 VIN- connects to RD2/PSP2 0 = C1 VIN- connects to RD1/PSP1 C2 VIN- connects to RD3/PSP3 CM2:CM0: Comparator Mode bits Figure 21-1 shows the Comparator modes and CM2:CM0 bit settings Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2-0 2002 Microchip Technology Inc. Preliminary DS41159B-page 245 PIC18FXX8 21.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 21-1 shows the eight possible modes. The TRISD register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay, shown in Electrical Specifications (Section 27.0). Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur. FIGURE 21-1: COMPARATOR I/O OPERATING MODES Comparators Off CM2:CM0 = 111 RD1/PSP1 C1 Off (Read as '0') D VINVIN+ Comparators Reset (POR Default Value) CM2:CM0 = 000 RD1/PSP1 A VINVIN+ RD0/PSP0 A RD0/PSP0 D C1 Off (Read as '0') RD3/PSP3 A VINVIN+ RD3/PSP3 C2 Off (Read as '0') D VINVIN+ RD2/PSP2 A RD2/PSP2 D C2 Off (Read as '0') Two Independent Comparators CM2:CM0 = 010 RD1/PSP1 A VINVIN+ Two Independent Comparators with Outputs CM2:CM0 = 011 RD1/PSP1 A A VINVIN+ RD0/PSP0 A C1 C1OUT RD0/PSP0 C1 C1OUT RE1/WR/AN6 RD3/PSP3 A VINVIN+ RD2/PSP2 A C2 C2OUT RD3/PSP3 RD2/PSP2 RE2/CS/AN7 A A VINVIN+ C2 C2OUT Two Common Reference Comparators CM2:CM0 = 100 RD1/PSP1 A VINVIN+ Two Common Reference Comparators with Outputs CM2:CM0 = 101 RD1/PSP1 A VINVIN+ RD0/PSP0 A C1 C1OUT RD0/PSP0 A RE1/WR/AN6 C1 C1OUT RD3/PSP3 A VINVIN+ RD2/PSP2 D C2 C2OUT RD3/PSP3 A VINVIN+ RD2/PSP2 D RE2/CS/AN7 One Independent Comparator with Output CM2:CM0 = 001 RD1/PSP1 RD0/PSP0 A A VINVIN+ C2 C2OUT Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 RD1/PSP1 A CIS = 0 CIS = 1 VINVIN+ C1 C1OUT RD0/PSP0 A RD3/PSP3 A C1 C1OUT RE1/WR/AN6 D RD3/PSP3 VINVIN+ RD2/PSP2 A C2 Off (Read as '0') CIS = 0 CIS = 1 VINVIN+ C2 C2OUT RD2/PSP2 D CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch DS41159B-page 246 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 21.2 Comparator Operation 21.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 21-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 21-2 represent the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 22.0 contains a detailed description of the Comparator Voltage Reference Module that provides this signal. The internal reference signal is used when comparators are in mode CM<2:0> = 110 (Figure 21-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 21.4 Comparator Response Time 21.3 Comparator Reference An external or internal reference signal may be used depending on the Comparator Operating mode. The analog signal present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 21-2). Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise the maximum delay of the comparators should be used (Section 27.0). FIGURE 21-2: SINGLE COMPARATOR 21.5 Comparator Outputs VIN+ VIN- + - Output VINVIN- VIN+ VIN+ The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RE1 and RE2 I/O pins. When enabled, multiplexors in the output path of the RE1 and RE2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 21-3 shows the comparator output block diagram. The TRISE bits will still function as an output enable/ disable for the RE1 and RE2 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input, according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Output utput 21.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s). 2002 Microchip Technology Inc. Preliminary DS41159B-page 247 PIC18FXX8 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RE1 or RE2 pin Bus Data Read CMCON Q EN D Set CMIF bit Q From Other Comparator D EN CL Read CMCON RESET 21.6 Comparator Interrupts Note: The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR registers) is the comparator interrupt flag. The CMIF bit must be reset by clearing `0'. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. . If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. DS41159B-page 248 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 21.7 Comparator Operation During SLEEP 21.8 Effects of a RESET A device RESET forces the CMCON register to its RESET state, causing the comparator module to be in the comparator RESET mode, CM<2:0> = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at RESET time. The comparators will be powered down during the RESET interval. When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from SLEEP mode, when enabled. While the comparator is powered up, higher SLEEP currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering SLEEP. If the device wakes up from SLEEP, the contents of the CMCON register are not affected. 21.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 21-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latchup condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 21-4: ANALOG INPUT MODEL VDD RS < 10k AIN VT = 0.6V RIC VA CPIN 5 pF VT = 0.6V I LEAKAGE 500 nA VSS Legend: CPIN VT I LEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage 2002 Microchip Technology Inc. Preliminary DS41159B-page 249 PIC18FXX8 TABLE 21-1: Name CMCON INTCON PIR2 PIE2 IPR2 PORTD LATD TRISD PORTE LATE TRISE Bit 7 REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 6 Bit 5 Bit 4 C1INV CVRSS INT0IE EEIF EEIE EEIP RD4 LATD4 -- -- Bit 3 CIS CVR3 RBIE BCLIF BCLIE BCLIP RD3 LATD3 -- -- -- Bit 2 CM2 CVR2 Bit 1 CM1 CVR1 Bit 0 CM0 CVR0 RBIF Value on POR Value on all other RESETS C2OUT C1OUT C2INV GIE/ GIEH -- -- -- RD7 PEIE/ GIEL CMIF(1) CMIE(1) CMIP (1) 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000u CVRCON CVREN CVROE CVRR TMR0IE -- -- -- RD5 LATD5 -- -- TMR0IF INT0IF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000 LVDIE TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000 LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111 RD2 LATD2 RE2 LATE2 RD1 LATD1 RE1 LATE1 RD0 LATD0 RE0 LATE0 TRISE0 x000 0000 u000 0000 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 ---- -000 ---- -000 ---- -xxx ---- -uuu 0000 -111 0000 -111 RD6 LATD7 LATD6 -- -- IBF(1) -- -- PORTD Data Direction Register OBF(1) IBOV(1) PSPMODE(1) TRISE2 TRISE1 Legend: x = unknown, u = unchanged, - = unimplemented, read as "0" Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear. DS41159B-page 250 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 22.0 Note: COMPARATOR VOLTAGE REFERENCE MODULE The Comparator Voltage Reference is only available on the PIC18F448 and PIC18F458. 22.1 Configuring the Comparator Voltage Reference The Comparator Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Comparator Voltage Reference are as follows. This module is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 22-1. The block diagram is shown in Figure 22-1. The comparator and reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-, that are multiplexed with RA3 and RA2. The comparator reference supply voltage is controlled by the CVRSS bit. EQUATION 22-1: If CVRR = 1: CVREF = (CVR<3:0>/24) x CVRSRC where: CVRSS = 1, CVRSRC = (VREF+) - (VREF-) CVRSS = 0, CVRSRC = VDD - VSS EQUATION 22-2: If CVRR = 0: CVREF = (CVRSRC x 1/4) + (CVR<3:0>/32) x CVRSRC where: CVRSS = 1, CVRSRC = (VREF+) - (VREF-) CVRSS = 0, CVRSRC = VDD - VSS The settling time of the Comparator Voltage Reference must be considered when changing the RA0/AN0/CVREF output (see Table 27-4 in Section 27.2). REGISTER 22-1: CVRCON REGISTER R/W-0 CVREN bit 7 R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin 0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.625 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VDD - VSS 0 = Comparator reference source CVRSRC = (VREF+) - (VREF-) CVR<3:0>: Comparator VREF Value Selection 0 CVR3:CVR0 15 bits When CVRR = 1: CVREF = (CVR3:CVR0/24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (CVR3:CVR0/32) * (CVRSRC) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3-0 2002 Microchip Technology Inc. Preliminary DS41159B-page 251 PIC18FXX8 FIGURE 22-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ 16 Stages R R R R CVRR 8R CVRSS = 0 CVRSS = 1 RA2/AN2VREFCVR3 (From CVRCON<3:0>) CVR0 CVRSS = 0 CVREN CVRSS = 1 8R RA0/AN0/CVREF or CVREF of Comparator 16-to-1 Analog MUX 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a RESET The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 22-1) keep VREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the VREF output changes with fluctuations in that source. The absolute accuracy of the voltage reference can be found in Section 27.0. A device RESET disables the voltage reference by clearing bit CVREN (CVRCON register). This RESET also disconnects the reference from the RA2 pin by clearing bit CVROE (CVRCON register) and selects the high voltage range by clearing bit CVRR (CVRCON register). The CVRSS value select bits, CVRCON<3:0>, are also cleared. 22.5 Connection Considerations 22.3 Operation During SLEEP When the device wakes up from SLEEP through an interrupt or a Watchdog Timer Time-out, the contents of the CVRCON register are not affected. To minimize current consumption in SLEEP mode, the voltage reference should be disabled. The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA0/AN0 pin if the TRISA<0> bit is set and the CVROE bit (CVRCON<6>) is set. Enabling the voltage reference output onto the RA0/AN0 pin, with an input signal present, will increase current consumption. Connecting RA0/AN0 as a digital output with CVRSS enabled, will also increase current consumption. The RA0/AN0 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 22-2 shows an example buffering technique. DS41159B-page 252 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE CVREF Module R(1) RA0/AN0 * Voltage Reference Output Impedance + - * CVREF Output Note 1: R is dependent upon the voltage reference configuration CVRCON<3:0> and CVRCON<5>. TABLE 22-1: Name CVRCON CMCON TRISA REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 6 Bit 5 CVRR C2INV Bit 4 CVRSS C1INV Bit 3 CVR3 CIS Bit 2 CVR2 CM2 Bit 1 CVR1 CM1 Bit 0 CVR0 CM0 Value on POR Value on all other RESETS Bit 7 CVREN CVROE C2OUT -- C1OUT 0000 0000 0000 0000 0000 0000 0000 0000 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 -111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as "0". Shaded cells are not used with the comparator voltage reference. 2002 Microchip Technology Inc. Preliminary DS41159B-page 253 PIC18FXX8 NOTES: DS41159B-page 254 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 23.0 LOW VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks" before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower than the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be "turned off" by the software, which minimizes the current consumption for the device. Figure 23-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shutdown the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference TB - TA is the total time for shutdown. The block diagram for the LVD module is shown in Figure 23-2. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 23-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). FIGURE 23-1: TYPICAL LOW VOLTAGE DETECT APPLICATION Voltage VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage TB Time TA 2002 Microchip Technology Inc. Preliminary DS41159B-page 255 PIC18FXX8 FIGURE 23-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM VDD LVDIN LVD3:LVD0 LVDCON Register 16 to 1 MUX LVDIF LVDEN Internally Generated Reference Voltage The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input pin LVDIN to one input of the comparator (Figure 23-3). The other input is connected to the internally generated voltage reference (parameter D423 in Section 27.2). This gives users flexibility, because it allows them to configure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 23-3: LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD LVD3:LVD0 LVDCON Register LVDEN LVD LVDIN Externally Generated Trip Point 16 to 1 MUX VxEN BODEN EN BGAP DS41159B-page 256 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 23.1 Control Register The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry. REGISTER 23-1: LVDCON REGISTER U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3 R/W-1 LVDL2 R/W-0 LVDL1 R/W-1 LVDL0 bit 0 bit 7-6 bit 5 Unimplemented: Read as '0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V min. - 4.77V max. 1101 = 4.2V min. - 4.45V max. 1100 = 4.0V min. - 4.24V max. 1011 = 3.8V min. - 4.03V max. 1010 = 3.6V min. - 3.82V max. 1001 = 3.5V min. - 3.71V max. 1000 = 3.3V min. - 3.50V max. 0111 = 3.0V min. - 3.18V max. 0110 = 2.8V min. - 2.97V max. 0101 = 2.7V min. - 2.86V max. 0100 = 2.5V min. - 2.65V max. 0011 = 2.4V min. - 2.54V max. 0010 = 2.2V min. - 2.33V max. 0001 = 2.0V min. - 2.12V max. 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. bit 4 bit 3-0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41159B-page 257 PIC18FXX8 23.2 Operation Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to set up the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD trip point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits). 2. 3. 4. 5. 6. Figure 23-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 23-4: CASE 1: LOW VOLTAGE DETECT WAVEFORMS LVDIF may not be set VDD . VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS41159B-page 258 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 23.2.1 REFERENCE VOLTAGE SET POINT 23.3 Operation During SLEEP The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 23-4. When enabled, the LVD circuitry continues to operate during SLEEP. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wake-up from SLEEP. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 23.4 Effects of a RESET A device RESET forces all registers to their RESET state. This forces the LVD module to be turned off. 23.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter D022B. 2002 Microchip Technology Inc. Preliminary DS41159B-page 259 PIC18FXX8 NOTES: DS41159B-page 260 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 24.0 SPECIAL FEATURES OF THE CPU SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options. There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * OSC Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-Circuit Serial Programming All PIC18FXX8 devices have a Watchdog Timer, which is permanently enabled via the configuration bits or software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Powerup Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. 24.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h - 3FFFFFh), which can only be accessed using Table Reads and Table Writes. Programming the configuration registers is done in a manner similar to programming the FLASH memory. The EECON1 register WR bit starts a self-timed write to the configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointed to the configuration register sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. TABLE 24-1: File Name CONFIGURATION BITS AND DEVICE IDS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300001h 300002h 300003h 300006h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFEh 3FFFFFh CONFIG1H CONFIG2L CONFIG2H CONFIG4L CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H DEVID1 DEVID2 -- -- -- DEBUG -- CPD -- WRTD -- -- DEV2 DEV10 -- -- -- -- -- CPB -- WRTB -- EBTRB DEV1 DEV9 OSCSEN -- -- -- -- -- -- WRTC -- -- DEV0 DEV8 -- -- -- -- -- -- -- -- -- -- REV4 DEV7 -- BORV1 WDTPS2 -- CP3 -- WRT3 -- EBTR3 -- REV3 DEV6 FOSC2 BORV0 WDTPS1 LVP CP2 -- WRT2 -- EBTR2 -- REV2 DEV5 FOSC1 BOREN WDTPS0 -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4 FOSC0 PWRTEN WDTEN STVREN CP0 -- WRT0 -- EBTR0 -- REV0 DEV3 --1- -111 ---- 1111 ---- 1111 1--- -1-1 ---- 1111 11-- ------- 1111 111- ------- 1111 -1-- ---- (1) 0000 1000 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: See Register 24-11 for DEVID1 values. 2002 Microchip Technology Inc. Preliminary DS41159B-page 261 PIC18FXX8 REGISTER 24-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 300001h) U-0 -- bit 7 bit 7-6 bit 5 Unimplemented: Read as `0' OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Oscillator system clock switch option is enabled (oscillator switching is enabled) Unimplemented: Read as `0' FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/ OSC2 configured as RA6 110 = HS oscillator with PLL enabled/clock frequency = (4 x FOSC) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide-by-4 clock output 011 = RC oscillator 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- R/P-1 OSCSEN U-0 -- U-0 -- R/P-1 FOSC2 R/P-1 FOSC1 R/P-1 FOSC0 bit 0 bit 4-3 bit 2-0 REGISTER 24-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h) U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 BOREN R/P-1 PWRTEN bit 0 bit 7-4 bit 3-2 bit 1 bit 0 Unimplemented: Read as `0' BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOREN: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS41159B-page 262 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 24-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h) U-0 -- bit 7 bit 7-4 bit 3-1 U-0 -- U-0 -- U-0 -- R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN bit 0 Unimplemented: Read as `0' WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 Note: The Watchdog Timer postscale select bits configuration used in the PIC18FXXX devices has changed from the configuration used in the PIC18CXXX devices. bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 24-4: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h) R/P-1 DEBUG bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 LVP U-0 -- R/P-1 STVREN bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. Unimplemented: Read as `0' LVP: Low Voltage ICSP Enable bit 1 = Low Voltage ICSP enabled 0 = Low Voltage ICSP disabled Unimplemented: Read as `0' STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed bit 6-3 bit 2 bit 1 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 263 PIC18FXX8 REGISTER 24-5: CONFIGURATION REGISTER 5 LOW (CONFIG5L: BYTE ADDRESS 300008h) U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as `0' CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code protected 0 = Block 3 (006000-007FFFh) code protected CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code protected 0 = Block 2 (004000-005FFFh) code protected CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code protected 0 = Block 1 (002000-003FFFh) code protected CP0: Code Protection bit 1 = Block 0 (000200-001FFFh) not code protected 0 = Block 0 (000200-001FFFh) code protected Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/C-1 CP3(1) R/C-1 CP2(1) R/C-1 CP1 R/C-1 CP0 bit 0 bit 2 bit 1 bit 0 REGISTER 24-6: CONFIGURATION REGISTER 5 HIGH (CONFIG5H: BYTE ADDRESS 300009h) R/C-1 CPD bit 7 R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code protected 0 = Data EEPROM code protected CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0001FFh) not code protected 0 = Boot Block (000000-0001FFh) code protected Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed bit 6 bit 5-0 DS41159B-page 264 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 24-7: CONFIGURATION REGISTER 6 LOW (CONFIG6L: BYTE ADDRESS 30000Ah) U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as `0' WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write protected 0 = Block 3 (006000-007FFFh) write protected WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write protected 0 = Block 2 (004000-005FFFh) write protected WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) not write protected 0 = Block 1 (002000-003FFFh) write protected WRT0: Write Protection bit 1 = Block 0 (000200-001FFFh) not write protected 0 = Block 0 (000200-001FFFh) write protected Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 WRT3(1) R/P-1 WRT2(1) R/P-1 WRT1 R/P-1 WRT0 bit 0 bit 2 bit 1 bit 0 REGISTER 24-8: CONFIGURATION REGISTER 6 HIGH (CONFIG6H: BYTE ADDRESS 30000Bh) R/P-1 WRTD bit 7 R/P-1 WRTB R-1 WRTC U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write protected 0 = Data EEPROM write protected WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0001FFh) not write protected 0 = Boot Block (000000-0001FFh) write protected WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write protected 0 = Configuration registers (300000-3000FFh) write protected Note: This bit is read only, and cannot be changed in User mode. bit 6 bit 5 bit 4-0 Unimplemented: Read as `0' Legend: R = Readable bit P =Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed 2002 Microchip Technology Inc. Preliminary DS41159B-page 265 PIC18FXX8 REGISTER 24-9: CONFIGURATION REGISTER 7 LOW (CONFIG7L: BYTE ADDRESS 30000Ch) U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as `0' EBTR3: Table Read Protection bit(1) 1 = Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks 0 = Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks EBTR0: Table Read Protection bit 1 = Block 0 (000200-001FFFh) not protected from Table Reads executed in other blocks 0 = Block 0 (000200-001FFFh) protected from Table Reads executed in other blocks Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 EBTR3(1) R/P-1 EBTR2(1) R/P-1 EBTR1 R/P-1 EBTR0 bit 0 bit 2 bit 1 bit 0 REGISTER 24-10: CONFIGURATION REGISTER 7 HIGH (CONFIG7H: BYTE ADDRESS 30000Dh) U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks 0 = Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks Unimplemented: Read as `0' Legend: R = Readable bit P =Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R/P-1 EBTRB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 bit 5-0 DS41159B-page 266 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 REGISTER 24-11: DEVICE ID REGISTER 1 FOR PIC18FXX8 DEVICE (DEVID1: BYTE ADDRESS 3FFFFEh) R DEV2 bit 7 bit 7-5 DEV2:DEV0: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number REV4:REV0: Revision ID bits These bits are used to indicate the device revision Legend: R = Readable bit P =Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0 bit 4-0 REGISTER 24-12: DEVICE ID REGISTER 2 FOR PIC18FXX8 DEVICE (DEVID2: BYTE ADDRESS 3FFFFFh) R DEV10 bit 7 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number Legend: R = Readable bit P =Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0 2002 Microchip Technology Inc. Preliminary DS41159B-page 267 PIC18FXX8 24.2 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/ CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the RCON register will be cleared upon a WDT time-out. The Watchdog Timer is enabled/disabled by a device configuration bit. If the WDT is enabled, software execution may not disable this function. When the WDTEN configuration bit is cleared, the SWDTEN bit enables/ disables the operation of the WDT. The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT postscaler may be assigned using the configuration bits. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT and prevent it from timing out and generating a device RESET condition. Note: When a CLRWDT instruction is executed and the postscaler is assigned to the WDT, the postscaler count will be cleared, but the postscaler assignment is not changed. 24.2.1 CONTROL REGISTER Register 24-13 shows the WDTCON register. This is a readable and writable register, which contains a control bit that allows software to override the WDT enable configuration bit, only when the configuration bit has disabled the WDT. REGISTER 24-13: WDTCON REGISTER U-0 -- bit 7 bit 7-1 bit 0 Unimplemented: Read as '0' SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = `0' Legend: R = Readable bit W = Writable bit - n = Value at POR reset U = Unimplemented bit, read as `0' U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN bit 0 DS41159B-page 268 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 24.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming, by the value written to the CONFIG2H configuration register. FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8 - to - 1 MUX WDTPS2:WDTPS0 WDTEN Configuration bit SWDTEN bit WDT Time-out Note: WDPS2:WDPS0 are bits in register CONFIG2H. TABLE 24-2: Name CONFIG2H RCON WDTCON SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 -- IPEN -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- RI -- Bit 3 WDTPS2 TO -- Bit 2 WDTPS2 PD -- Bit 1 WDTPS0 POR -- Bit 0 WDTEN BOR SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. 2002 Microchip Technology Inc. Preliminary DS41159B-page 269 PIC18FXX8 24.3 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared, but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and will cause a "wake-up". The TO and PD bits in the RCON register can be used to determine the cause of the device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared, if a WDT time-out occurred (and caused wake-up). When the SLEEP instruction is being executed, the next instruction (PC + 2) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 24.3.1 WAKE-UP FROM SLEEP 24.3.2 WAKE-UP USING INTERRUPTS The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a peripheral interrupt. When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. The following peripheral interrupts can wake the device from SLEEP: PSP read or write. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. TMR3 interrupt. Timer3 must be operating as an asynchronous counter. 4. CCP Capture mode interrupt. 5. Special event trigger (Timer1 in Asynchronous mode using an external clock). 6. MSSP (START/STOP) bit detect interrupt. 7. MSSP transmit or receive in Slave mode (SPI/I2C). 8. USART RX or TX (Synchronous Slave mode). 9. A/D conversion (when A/D clock source is RC). 10. EEPROM write operation complete. 11. LVD interrupt. Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. 1. 2. DS41159B-page 270 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 24-2: OSC1 CLKO(4) INT pin INTF flag (INTCON<1>) GIEH bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+2 Inst(PC + 2) SLEEP PC+4 PC+4 Inst(PC + 4) Inst(PC + 2) Dummy Cycle PC + 4 0008h Inst(0008h) Dummy Cycle 000Ah Inst(000Ah) Inst(0008h) Processor in SLEEP Interrupt Latency(3) TOST(2) WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Note 1: 2: 3: 4: XT, HS or LP Oscillator mode assumed. GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes. CLKO is not available in these Osc modes, but shown here for timing reference. 2002 Microchip Technology Inc. Preliminary DS41159B-page 271 PIC18FXX8 24.4 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: * Code Protect bit (CPn) * Write Protect bit (WRTn) * External Block Table Read bit (EBTRn) Figure 24-3 shows the program memory organization for 16- and 32-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 24-3. The overall structure of the code protection on the PIC18 FLASH devices differs significantly from other PICmicro devices. The user program memory is divided into five blocks. One of these is a boot block of 512 bytes. The remainder of the memory is divided into four blocks on binary boundaries. FIGURE 24-3: CODE PROTECTED PROGRAM MEMORY FOR PIC18F2X8/4X8 MEMORY SIZE/DEVICE Block Code Protection Controlled By: 16 Kbytes (PIC18FX48) Boot Block 32 Kbytes (PIC18FX58) Boot Block Address Range 000000h 0001FFh 000200h CPB, WRTB, EBTRB Block 0 Block 0 001FFFh 002000h CP0, WRT0, EBTR0 Block 1 Block 1 003FFFh 004000h Block 2 005FFFh 006000h Block 3 007FFFh 008000h CP1, WRT1, EBTR1 Unimplemented Read 0s Unimplemented Read 0s CP2, WRT2, EBTR2 CP3, WRT3, EBTR3 Unimplemented Read 0s Unimplemented Read 0s (Unimplemented Memory Space) 1FFFFFh TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS Bit 7 -- CPD -- WRTD -- -- Bit 6 -- CPB -- WRTB -- EBTRB Bit 5 -- -- -- WRTC -- -- Bit 4 -- -- -- -- -- -- Bit 3 CP3 -- WRT3 -- EBTR3 -- Bit 2 CP2 -- WRT2 -- EBTR2 -- Bit 1 CP1 -- WRT1 -- EBTR1 -- Bit 0 CP0 -- WRT0 -- EBTR0 -- File Name 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H Legend: Shaded cells are unimplemented. DS41159B-page 272 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 24.4.1 PROGRAM MEMORY CODE PROTECTION Note: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. The user memory may be read to or written from any location using the Table Read and Table Write instructions. The device ID may be read with Table Reads. The configuration registers may be read and written with the Table Read and Table Write instructions. In User mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from Table Writes if the WRTn configuration bit is `0'. The EBTRn bits control Table Reads. For a block of user memory with the EBTRn bit set to `0', a Table Read instruction that executes from within that block is allowed to read. A Table Read instruction that executes from a location outside of that block is not allowed to read, and will result in reading `0's. Figures 24-4 through 24-6 illustrate Table Write and Table Read protection. FIGURE 24-4: TABLE WRITE (WRTn) DISALLOWED Program Memory 000000h 0001FFh 000200h WRTB,EBTRB = 11 Configuration Bit Settings Register Values TBLPTR = 000FFF WRT0,EBTR0 = 01 PC = 001FFE TBLWT * 001FFFh 002000h WRT1,EBTR1 = 11 003FFFh 004000h PC = 004FFE TBLWT * 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: All Table Writes disabled to Blockn whenever WRTn = `0'. WRT2,EBTR2 = 11 2002 Microchip Technology Inc. Preliminary DS41159B-page 273 PIC18FXX8 FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Program Memory 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 000FFF WRT0,EBTR0 = 10 001FFFh 002000h PC = 002FFE TBLRD * 003FFFh 004000h WRT2,EBTR2 = 11 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = `0'. TABLAT register returns a value of "0". WRT1,EBTR1 = 11 Configuration Bit Settings Register Values FIGURE 24-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Program Memory 000000h WRTB,EBTRB = 11 0001FFh 000200h Configuration Bit Settings Register Values TBLPTR = 000FFF PC = 001FFE TBLRD * 001FFFh 002000h WRT0,EBTR0 = 10 WRT1,EBTR1 = 11 003FFFh 004000h WRT2,EBTR2 = 11 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: Table Reads permitted within Blockn, even when EBTRBn = `0'. TABLAT register returns the value of the data at the location TBLPTR. DS41159B-page 274 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 24.4.2 DATA EEPROM CODE PROTECTION To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies. The Microchip In-Circuit Debugger (ICD) used with the PIC18FXXX microcontrollers is the MPLAB(R) ICD 2. The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM, regardless of the protection bit settings. 24.4.3 CONFIGURATION REGISTER PROTECTION 24.8 Low Voltage ICSP Programming The configuration registers can be write protected. The WRTC bit controls protection of the configuration registers. In User mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 24.5 ID Locations Eight memory locations (200000h - 200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are accessible during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code protected. The LVP bit configuration register CONFIG4L enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the MCLR/VPP pin. To enter Programming mode, VDD must be applied to the RB5/PGM, provided the LVP bit is set. The LVP bit defaults to a (`1') from the factory. Note 1: The High Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O pin. 3: When using Low Voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 5 in the TRISB register must be cleared to disable the pull-up on RB5 and ensure the proper operation of the device. If Low Voltage Programming mode is not used, the LVP bit can be programmed to a '0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on MCLR/VPP. The LVP bit can only be charged when using high voltage on MCLR. It should be noted that once the LVP bit is programmed to 0, only the High Voltage Programming mode is available and only High Voltage Programming mode can be used to program the device. When using Low Voltage ICSP, the part must be supplied 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to off-state. For all other cases of Low Voltage ICSP, the part may be programmed at the normal operating voltage. This means unique user IDs, or user code can be reprogrammed or added. 24.6 In-Circuit Serial Programming PIC18FXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 24.7 In-Circuit Debugger When the DEBUG bit in configuration register CONFIG4L is programmed to a '0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some of the resources are not available for general use. Resources used include 2 I/O pins, stack locations, program memory and data memory. For more information on the resources required, see the User's Guide for the In-Circuit Debugger you are using. 2002 Microchip Technology Inc. Preliminary DS41159B-page 275 PIC18FXX8 NOTES: DS41159B-page 276 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 25.0 INSTRUCTION SET SUMMARY The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the Call or Return instructions (specified by `s') * The mode of the Table Read and Table Write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for three double-word instructions. These three instructions were made double-word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are 1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 25-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 25-2, lists the instructions recognized by the Microchip Assembler (MPASMTM). Section 25.2 provides a description of each instruction. The PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. Each single word instruction is a 16-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 25-2 lists byte-oriented, bit-oriented, literal and control operations. Table 25-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator 'f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') 25.1 READ-MODIFY-WRITE OPERATIONS The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a "clrf PORTB" instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag would be cleared. 2002 Microchip Technology Inc. DS41159B-page 277 PIC18FXX8 TABLE 25-1: Field a OPCODE FIELD DESCRIPTIONS Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7) Bank Select Register. Used to select the current RAM bank. Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f. Destination either the WREG register or the specified register file location 8-bit Register file address (0x00 to 0xFF) 12-bit Register file address (0x000 to 0xFFF). This is the source address. 12-bit Register file address (0x000 to 0xFFF). This is the destination address. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) Label name The mode of the TBLPTR register for the Table Read and Table Write instructions. Only used with Table Read and Table Write instructions: No change to register (such as TBLPTR with Table Reads and Writes) Post-Increment register (such as TBLPTR with Table Reads and Writes) Post-Decrement register (such as TBLPTR with Table Reads and Writes) Pre-Increment register (such as TBLPTR with Table Reads and Writes) The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions Product of Multiply high byte Product of Multiply low byte Fast Call/Return mode select bit; s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) Unused or Unchanged Working register (accumulator) Don't care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 21-bit Table Pointer (points to a Program Memory location) 8-bit Table Latch Top-of-Stack Program Counter Program Counter Low Byte Program Counter High Byte Program Counter High Byte Latch Program Counter Upper Byte Latch Global Interrupt Enable bit Watchdog Timer Time-out bit Power-down bit ALU status bits Carry, Digit Carry, Zero, Overflow, Negative Optional Contents Assigned to Register bit field In the set of User defined term (font is courier) bbb BSR d dest f fs fd k label mm * *+ *+* n PRODH PRODL s u WREG x TBLPTR TABLAT TOS PC PCL PCH PCLATH PCLATU GIE WDT TO PD C, DC, Z, OV, N [ ( <> italics ] ) DS41159B-page 278 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 87 OPCODE d a 0 f (FILE #) ADDWF MYREG, W, B Example Instruction d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 0 f (Source FILE #) 0 f (Destination FILE #) MOVFF MYREG1, MYREG2 f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B OPCODE b (BIT #) a b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 8 7 k (literal) 0 MOVLW 0x7F 87 n<7:0> (literal) 0 GOTO Label 12 11 n<19:8> (literal) 0 n = 20-bit immediate value 15 OPCODE 15 12 11 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 11 10 n<10:0> (literal) 87 n<7:0> (literal) 0 BC MYFUNC 87 S n<7:0> (literal) 0 CALL MYFUNC 0 0 BRA MYFUNC 2002 Microchip Technology Inc. DS41159B-page 279 PIC18FXX8 TABLE 25-2: Mnemonic, Operands PIC18FXXX INSTRUCTION SET 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF 1 f, d, a Add WREG and f 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF 1 f, d, a AND WREG with f 0001 01da ffff ffff Z, N 1,2 Clear f CLRF 1 f, a 0110 101a ffff ffff Z 2 COMF 1 f, d, a Complement f 0001 11da ffff ffff Z, N 1, 2 Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None CPFSEQ f, a 4 Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None CPFSGT f, a 4 Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None CPFSLT f, a 1, 2 DECF 1 f, d, a Decrement f 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF 1 f, d, a Increment f 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ 1 (2 or 3) 0011 11da ffff ffff None f, d, a Increment f, Skip if 0 4 INFSNZ 1 (2 or 3) 0100 10da ffff ffff None f, d, a Increment f, Skip if Not 0 1, 2 IORWF 1 f, d, a Inclusive OR WREG with f 0001 00da ffff ffff Z, N 1, 2 MOVF 1 f, d, a Move f 0101 00da ffff ffff Z, N 1 MOVFF 2 fs, fd Move fs (source) to 1st word 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff Move WREG to f MOVWF f, a 1 0110 111a ffff ffff None f, a Multiply WREG with f MULWF 1 0000 001a ffff ffff None f, a Negate f NEGF 1 0110 110a ffff ffff C, DC, Z, OV, N 1, 2 f, d, a Rotate Left f through Carry RLCF 1 0011 01da ffff ffff C, Z, N f, d, a Rotate Left f (No Carry) RLNCF 1 0100 01da ffff ffff Z, N 1, 2 f, d, a Rotate Right f through Carry RRCF 1 0011 00da ffff ffff C, Z, N f, d, a Rotate Right f (No Carry) RRNCF 1 0100 00da ffff ffff Z, N f, a Set f SETF 1 0110 100a ffff ffff None SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N 1, 2 borrow f, d, a Subtract WREG from f SUBWF 1 0101 11da ffff ffff C, DC, Z, OV, N SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N 1, 2 borrow f, d, a Swap nibbles in f SWAPF 1 0011 10da ffff ffff None 4 Test f, skip if 0 TSTFSZ f, a 1 (2 or 3) 0110 011a ffff ffff None 1, 2 f, d, a Exclusive OR WREG with f XORWF 1 0001 10da ffff ffff Z, N BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. DS41159B-page 280 2002 Microchip Technology Inc. PIC18FXX8 TABLE 25-2: Mnemonic, Operands PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 LSb nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s Status Affected Notes CONTROL OPERATIONS BC n Branch if Carry BN n Branch if Negative BNC n Branch if Not Carry BNN n Branch if Not Negative BNOV n Branch if Not Overflow BNZ n Branch if Not Zero BOV n Branch if Overflow BRA n Branch Unconditionally BZ n Branch if Zero CALL n, s Call subroutine 1st word 2nd word CLRWDT -- Clear Watchdog Timer DAW -- Decimal Adjust WREG GOTO n Go to address 1st word 2nd word NOP -- No Operation NOP -- No Operation (Note 4) POP -- Pop top of return stack (TOS) PUSH -- Push top of return stack (TOS) RCALL n Relative Call RESET Software device RESET RETFIE s Return from interrupt enable None None None None None None None None None None TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP -- Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. 2002 Microchip Technology Inc. DS41159B-page 281 PIC18FXX8 TABLE 25-2: Mnemonic, Operands PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. DS41159B-page 282 2002 Microchip Technology Inc. PIC18FXX8 25.2 ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Instruction Set ADD literal to W [ label ] ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z 0000 1111 kkkk kkkk ADDWF k Syntax: Operands: ADD W to f [ label ] ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z 0010 01da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: The contents of W are added to the 8-bit literal 'k' and the result is placed in W. 1 1 Q2 Read literal 'k' ADDLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x15 Q4 Write to W Add W to register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR is used. 1 1 Q2 Read register 'f' ADDWF Words: Cycles: Q Cycle Activity: Q1 Decode Example: W W = = Before Instruction 0x10 0x25 Q3 Process Data REG, W Q4 Write to destination After Instruction Example: W REG W REG = = = = Before Instruction 0x17 0xC2 0xD9 0xC2 After Instruction 2002 Microchip Technology Inc. DS41159B-page 283 PIC18FXX8 ADDWFC Syntax: Operands: ADD W and Carry bit to f [ label ] ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N, OV, C, DC, Z 0010 00da ffff ffff ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. k W N, Z 0000 1011 kkkk kkkk f [,d [,a]] k Operation: Status Affected: Encoding: Description: Add W, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in data memory location 'f'. If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden. 1 1 The contents of W are ANDed with the 8-bit literal 'k'. The result is placed in W. 1 1 Q2 Read literal 'k' ANDLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x5F Q4 Write to W Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q2 Read register 'f' ADDWFC Q3 Process Data REG, W Q4 Write to destination Before Instruction W W = = 0xA3 0x03 After Instruction Example: Carry bit = REG = W = Before Instruction 1 0x02 0x4D 0 0x02 0x50 After Instruction Carry bit = REG = W = DS41159B-page 284 2002 Microchip Technology Inc. PIC18FXX8 ANDWF Syntax: Operands: AND W with f [ label ] ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z 0001 01da ffff ffff BC f [,d [,a]] Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Carry [ label ] BC n -128 n 127 if carry bit is '1' (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn Operation: Status Affected: Encoding: Description: The contents of W are AND'ed with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden (default). 1 1 Q2 Read register 'f' ANDWF If the Carry bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q3 Process Data REG, W Q4 Write to destination Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: W REG W REG = = = = Before Instruction 0x17 0xC2 0x02 0xC2 If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BC JUMP Q4 No operation After Instruction Example: PC Before Instruction = = = = = address (HERE) 1; address (JUMP) 0; address (HERE+2) After Instruction If Carry PC If Carry PC 2002 Microchip Technology Inc. DS41159B-page 285 PIC18FXX8 BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 255 0b7 a [0,1] 0 f None 1001 bbba ffff ffff BN f,b[,a] Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Negative [ label ] BN n -128 n 127 if negative bit is '1' (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn Operation: Status Affected: Encoding: Description: Bit 'b' in register 'f' is cleared. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' BCF Words: Cycles: Q Cycle Activity: Q1 Decode If the Negative bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q3 Process Data FLAG_REG, 7 Q4 Write register 'f' Q Cycle Activity: If Jump: Q1 Decode Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: Before Instruction FLAG_REG = 0xC7 No operation After Instruction FLAG_REG = 0x47 If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BN Jump Q4 No operation Example: PC Before Instruction = = = = = address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Negative PC If Negative PC DS41159B-page 286 2002 Microchip Technology Inc. PIC18FXX8 BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry [ label ] BNC -128 n 127 if carry bit is '0' (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn BNN Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Negative [ label ] BNN -128 n 127 if negative bit is '0' (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn n n If the Carry bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) If the Negative bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNC Jump Q4 No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNN Jump Q4 No operation Example: PC Example: PC Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) After Instruction If Carry PC If Carry PC After Instruction If Negative PC If Negative PC 2002 Microchip Technology Inc. DS41159B-page 287 PIC18FXX8 BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow [ label ] BNOV -128 n 127 if overflow bit is '0' (PC) + 2 + 2n PC None 1110 0101 nnnn nnnn BNZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Zero [ label ] BNZ -128 n 127 if zero bit is '0' (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn n n If the Overflow bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) If the Zero bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNOV Jump Q4 No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNZ Jump Q4 No operation Example: PC Example: PC Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) After Instruction If Overflow PC If Overflow PC After Instruction If Zero PC If Zero PC DS41159B-page 288 2002 Microchip Technology Inc. PIC18FXX8 BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] BRA n -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn BSF Syntax: Operands: Bit Set f [ label ] BSF 0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff f,b[,a] Operation: Status Affected: Encoding: Description: Add the 2's complement number '2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2 Read literal 'n' No operation Words: Cycles: Q Cycle Activity: Q1 Decode No operation Bit 'b' in register 'f' is set. If `a' is 0, Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' BSF Words: Cycles: Q3 Process Data No operation Q4 Write to PC No operation Q Cycle Activity: Q1 Decode Q3 Process Data FLAG_REG, 7 Q4 Write register 'f' Example: Example: PC HERE BRA Jump Before Instruction FLAG_REG = = 0x0A 0x8A Before Instruction = = address (HERE) address (Jump) After Instruction FLAG_REG After Instruction PC 2002 Microchip Technology Inc. DS41159B-page 289 PIC18FXX8 BTFSC Syntax: Operands: Bit Test File, Skip if Clear [ label ] BTFSC f,b[,a] 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff BTFSS Syntax: Operands: Bit Test File, Skip if Set [ label ] BTFSS f,b[,a] 0 f 255 0b7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: If bit 'b' in register 'f' is 0, then the next instruction is skipped. If bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' If bit 'b' in register 'f' is 1, then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q Cycle Activity: Q1 Decode Q2 Read register 'f' Q4 No operation If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE FALSE TRUE Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE FALSE TRUE Q4 No operation No operation No operation No operation BTFSC : : No operation No operation BTFSS : : Example: FLAG, 1 Example: FLAG, 1 Before Instruction PC = = = = = address (HERE) 0; address (TRUE) 1; address (FALSE) Before Instruction PC = = = = = address (HERE) 0; address (FALSE) 1; address (TRUE) After Instruction If FLAG<1> PC If FLAG<1> PC After Instruction If FLAG<1> PC If FLAG<1> PC DS41159B-page 290 2002 Microchip Technology Inc. PIC18FXX8 BTG Syntax: Operands: Bit Toggle f [ label ] BTG f,b[,a] 0 f 255 0b7 a [0,1] (f) f None 0111 bbba ffff ffff BOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Overflow [ label ] BOV -128 n 127 if overflow bit is '1' (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn n Operation: Status Affected: Encoding: Description: Bit 'b' in data memory location 'f' is inverted. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' BTG Words: Cycles: Q Cycle Activity: Q1 Decode If the Overflow bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q3 Process Data PORTC, 4 Q4 Write register 'f' Q Cycle Activity: If Jump: Q1 Decode Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: PORTC PORTC = = Before Instruction: 0111 0101 [0x75] 0110 0101 [0x65] No operation After Instruction: If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BOV JUMP Q4 No operation Example: PC Before Instruction = = = = = address (HERE) 1; address (JUMP) 0; address (HERE+2) After Instruction If Overflow PC If Overflow PC 2002 Microchip Technology Inc. DS41159B-page 291 PIC18FXX8 BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero [ label ] BZ n -128 n 127 if Zero bit is '1' (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn CALL Syntax: Operands: Operation: Subroutine Call [ label ] CALL k [,s] 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 If the Zero bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Subroutine call of entire 2 Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If 's' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then, the 20-bit value 'k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Read literal 'k'<7:0>, No operation HERE If No Jump: Q1 Decode Words: Q2 Read literal 'n' HERE Q3 Process Data BZ Jump Q4 No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Push PC to stack No operation CALL Q4 Read literal 'k'<19:8>, Write to PC No operation Example: PC Before Instruction = = = = = address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Zero PC If Zero PC No operation Example: PC = THERE,FAST Before Instruction address (HERE) address (THERE) address (HERE + 4) W BSR STATUS After Instruction PC = TOS = WS = BSRS = STATUSS= DS41159B-page 292 2002 Microchip Technology Inc. PIC18FXX8 CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f [label] CLRF 0 f 255 a [0,1] 000h f 1Z Z 0110 101a ffff ffff CLRWDT f [,a] Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100 Status Affected: Encoding: Description: Clears the contents of the specified register. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' CLRF CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. 1 1 Q2 No operation CLRWDT Words: Cycles: Q Cycle Activity: Q1 Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q3 Process Data FLAG_REG Q4 Write register 'f' Decode Example: Example: Before Instruction FLAG_REG = = 0x5A 0x00 Before Instruction WDT Counter = = = = = ? 0x00 0 1 1 After Instruction WDT Counter WDT Postscaler TO PD After Instruction FLAG_REG 2002 Microchip Technology Inc. DS41159B-page 293 PIC18FXX8 COMF Syntax: Operands: Complement f [ label ] COMF 0 f 255 d [0,1] a [0,1] ( f ) dest N, Z 0001 11da ffff ffff CPFSEQ f [,d [,a]] Syntax: Operands: Operation: Compare f with W, skip if f = W [ label ] CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff f [,a] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' COMF Words: Cycles: Q Cycle Activity: Q1 Decode Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If 'f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Q3 Process Data REG, W Q4 Write to destination Words: Cycles: Example: REG REG W = = = Before Instruction 0x13 0x13 0xEC After Instruction Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NEQUAL EQUAL Q4 No operation No operation No operation No operation CPFSEQ REG : : Example: Before Instruction PC Address W REG = = = = = = HERE ? ? After Instruction If REG PC If REG PC W; Address (EQUAL) W; Address (NEQUAL) DS41159B-page 294 2002 Microchip Technology Inc. PIC18FXX8 CPFSGT Syntax: Operands: Operation: Compare f with W, skip if f > W [ label ] CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff CPFSLT Syntax: Operands: Operation: Compare f with W, skip if f < W [ label ] CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff f [,a] f [,a] Status Affected: Encoding: Description: Status Affected: Encoding: Description: Compares the contents of data memory location 'f' to the contents of the W by performing an unsigned subtraction. If the contents of 'f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If the contents of 'f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected. If 'a' is 1, the BSR will not be overridden (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NLESS LESS Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NGREATER GREATER Q4 No operation No operation No operation No operation CPFSLT REG : : No operation No operation CPFSGT REG : : Example: Example: Before Instruction PC W = = < = = Address (HERE) ? W; Address (LESS) W; Address (NLESS) Before Instruction PC W = = > = = Address (HERE) ? W; Address (GREATER) W; Address (NGREATER) After Instruction If REG PC If REG PC After Instruction If REG PC If REG PC 2002 Microchip Technology Inc. DS41159B-page 295 PIC18FXX8 DAW Syntax: Operands: Operation: Decimal Adjust W Register [label] DAW None If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4>; Status Affected: Encoding: Description: C 0000 0000 0000 0111 DECF Syntax: Operands: Decrement f [ label ] DECF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z 0000 01da ffff ffff Operation: Status Affected: Encoding: Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Q2 Read register W DAW Decrement register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' DECF Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data CNT, Q4 Write to destination Q3 Process Data Q4 Write W Example: CNT Z CNT Z = = = = Example1: W C DC W C DC = = = = = = Before Instruction 0x01 0 0x00 1 Before Instruction 0xA5 0 0 0x05 1 0 After Instruction After Instruction Example 2: Before Instruction W C DC W C DC = = = = = = 0xCE 0 0 0x34 1 0 After Instruction DS41159B-page 296 2002 Microchip Technology Inc. PIC18FXX8 DECFSZ Syntax: Operands: Decrement f, skip if 0 [ label ] DECFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff DCFSNZ Syntax: Operands: Decrement f, skip if not 0 [ label ] DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of register 'f' are decremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE CONTINUE Q4 No operation No operation CNT LOOP If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE ZERO NZERO Q4 No operation No operation No operation No operation DECFSZ GOTO No operation No operation DCFSNZ : : TEMP Example: Example: Before Instruction PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2) Before Instruction TEMP = = = = = ? TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) After Instruction After Instruction TEMP If TEMP PC If TEMP PC 2002 Microchip Technology Inc. DS41159B-page 297 PIC18FXX8 GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch [ label ] GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 INCF Syntax: Operands: Increment f [ label ] INCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z 0010 10da ffff ffff Operation: Status Affected: Encoding: Description: GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range. The 20-bit value 'k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2 Words: Cycles: Q Cycle Activity: Q1 Decode The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' INCF Words: Q2 Read literal 'k'<7:0>, No operation Q3 No operation No operation Q4 Read literal 'k'<19:8>, Write to PC No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data CNT, Q4 Write to destination No operation Example: PC = GOTO THERE Example: CNT Z C DC CNT Z C DC = = = = = = = = After Instruction Address (THERE) Before Instruction 0xFF 0 ? ? 0x00 1 1 1 After Instruction DS41159B-page 298 2002 Microchip Technology Inc. PIC18FXX8 INCFSZ Syntax: Operands: Increment f, skip if 0 [ label ] INCFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff INFSNZ Syntax: Operands: Increment f, skip if not 0 [ label ] INFSNZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NZERO ZERO Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE ZERO NZERO Q4 No operation No operation No operation No operation INCFSZ : : CNT No operation No operation INFSNZ REG Example: Example: Before Instruction PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) Before Instruction PC REG If REG PC If REG PC = = Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) After Instruction After Instruction = = = 2002 Microchip Technology Inc. DS41159B-page 299 PIC18FXX8 IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k W N, Z 0000 1001 kkkk kkkk IORWF Syntax: Operands: Inclusive OR W with f [ label ] IORWF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z 0001 00da ffff ffff Operation: Status Affected: Encoding: Description: The contents of W are OR'ed with the eight-bit literal 'k'. The result is placed in W. 1 1 Q2 Read literal 'k' IORLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x35 Q4 Write to W Inclusive OR W with register 'f'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' IORWF Words: Example: W W = = Cycles: Q Cycle Activity: Q1 Decode Before Instruction 0x9A 0xBF Q3 Process Data RESULT, W Q4 Write to destination After Instruction Example: RESULT = W = Before Instruction 0x13 0x91 0x13 0x93 After Instruction RESULT = W = DS41159B-page 300 2002 Microchip Technology Inc. PIC18FXX8 LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Load FSR [ label ] LFSR f,k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk MOVF Syntax: Operands: Move f [ label ] MOVF f [,d [,a]] 0 f 255 d [0,1] a [0,1] f dest N, Z 0101 00da ffff ffff Operation: Status Affected: Encoding: Description: The 12-bit literal 'k' is loaded into the file select register pointed to by 'f'. 2 2 Q2 Read literal 'k' MSB Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write literal 'k' MSB to FSRfH Write literal 'k' to FSRfL The contents of register 'f' are moved to a destination dependent upon the status of 'd'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). Location 'f' can be anywhere in the 256 byte bank. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' MOVF Decode Read literal 'k' LSB Process Data Words: Cycles: Q Cycle Activity: Q1 Decode Example: FSR2H FSR2L LFSR 2, 0x3AB After Instruction = = 0x03 0xAB Q3 Process Data REG, W Q4 Write W Example: REG W Before Instruction = = = = 0x22 0xFF 0x22 0x22 After Instruction REG W 2002 Microchip Technology Inc. DS41159B-page 301 PIC18FXX8 MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f [ label ] MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Move literal to low nibble in BSR [ label ] k BSR None 0000 0001 kkkk kkkk MOVLB k 0 k 255 The 8-bit literal 'k' is loaded into the Bank Select Register (BSR). 1 1 Q2 Read literal 'k' The contents of source register 'fs' are moved to destination register 'fd'. Location of source 'fs' can be anywhere in the 4096 byte data space (000h to FFFh), and location of destination 'fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see page 77). Q3 Process Data Q4 Write literal 'k' to BSR Example: MOVLB 5 Before Instruction BSR register = = 0x02 0x05 After Instruction BSR register Words: Cycles: Q Cycle Activity: Q1 Decode 2 2 (3) Q2 Read register 'f' (src) No operation No dummy read Q3 Process Data No operation Q4 No operation Write register 'f' (dest) Decode Example: REG1 REG2 MOVFF REG1, REG2 Before Instruction = = = = 0x33 0x11 0x33, 0x33 After Instruction REG1 REG2 DS41159B-page 302 2002 Microchip Technology Inc. PIC18FXX8 MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Move literal to W [ label ] kW None 0000 1110 kkkk kkkk MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move W to f [ label ] MOVWF f [,a] 0 f 255 a [0,1] (W) f None 0110 111a ffff ffff MOVLW k 0 k 255 The eight-bit literal 'k' is loaded into W. 1 1 Q2 Read literal 'k' MOVLW Q3 Process Data 0x5A Q4 Write to W Move data from W to register 'f'. Location 'f' can be anywhere in the 256 byte bank. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' MOVWF Words: Cycles: Q Cycle Activity: Q1 Decode Example: W = After Instruction 0x5A Q3 Process Data REG Q4 Write register 'f' Example: W REG W REG = = = = Before Instruction 0x4F 0xFF 0x4F 0x4F After Instruction 2002 Microchip Technology Inc. DS41159B-page 303 PIC18FXX8 MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with W [ label ] MULLW k 0 k 255 (W) x k PRODH:PRODL None 0000 1101 kkkk kkkk MULWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply W with f [ label ] MULWF f [,a] 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of W and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible, but not detected. 1 1 Q2 Read literal 'k' Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write registers PRODH: PRODL An unsigned multiplication is carried out between the contents of W and the register file location 'f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and 'f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible, but not detected. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a'= 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode Example: W PRODH PRODL MULLW 0xC4 Q3 Process Data Q4 Write registers PRODH: PRODL Before Instruction = = = = = = 0xE2 ? ? 0xE2 0xAD 0x08 After Instruction W PRODH PRODL Example: W REG PRODH PRODL MULWF REG Before Instruction = = = = = = = = 0xC4 0xB5 ? ? 0xC4 0xB5 0x8A 0x94 After Instruction W REG PRODH PRODL DS41159B-page 304 2002 Microchip Technology Inc. PIC18FXX8 NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f [ label ] NEGF f [,a] 0 f 255 a [0,1] (f)+1f N, OV, C, DC, Z 0110 110a ffff ffff NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode No Operation [ label ] None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx NOP Location `f' is negated using two's complement. The result is placed in the data memory location 'f'. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' NEGF No operation. 1 1 Q2 No operation Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q3 Process Data REG, 1 Q4 Write register 'f' None. Example: REG REG = = Before Instruction 0011 1010 [0x3A] 1100 0110 [0xC6] After Instruction 2002 Microchip Technology Inc. DS41159B-page 305 PIC18FXX8 POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack [ label ] None (TOS) bit bucket None 0000 0000 0000 0110 PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description: Push Top of Return Stack [ label ] None (PC+2) TOS None 0000 0000 0000 0101 POP PUSH The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2 No operation POP GOTO The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows the user to implement a software stack by modifying TOS, and then push it onto the return stack. 1 1 Q2 PUSH PC+2 onto return stack PUSH Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode Q3 No operation Q4 No operation Q3 POP TOS value Q4 No operation Example: Example: NEW Before Instruction TOS PC 0x0031A2 0x014332 = = 0x00345A 0x000124 Before Instruction TOS Stack (1 level down) = = After Instruction PC TOS Stack (1 level down) = = = 0x000126 0x000126 0x00345A After Instruction TOS PC = = 0x014332 NEW DS41159B-page 306 2002 Microchip Technology Inc. PIC18FXX8 RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call [ label ] RCALL -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 1nnn nnnn nnnn RESET n Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Reset [ label ] None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 RESET Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2's complement number '2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2 Read literal 'n' Push PC to stack This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2 Start reset RESET Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: Registers = Flags* = After Instruction Q3 Process Data Q4 Write to PC Reset Value Reset Value No operation No operation HERE No operation RCALL Jump No operation Example: PC = PC = TOS = Before Instruction Address (HERE) Address (Jump) Address (HERE+2) After Instruction 2002 Microchip Technology Inc. DS41159B-page 307 PIC18FXX8 RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged. GIE/GIEH, PEIE/GIEL. 0000 0000 0001 000s RETLW Syntax: Operands: Operation: Return Literal to W [ label ] RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk RETFIE [s] Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2 No operation W is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2 Read literal 'k' No operation Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data No operation Q4 pop PC from stack, Write to W No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value Q3 No operation Q4 pop PC from stack Set GIEH or GIEL No operation No operation RETFIE 1 No operation No operation W = offset Begin table Example: After Interrupt End of table PC W BSR STATUS GIE/GIEH, PEIE/GIEL = = = = = TOS WS BSRS STATUSS 1 Before Instruction W W = = 0x07 value of kn After Instruction DS41159B-page 308 2002 Microchip Technology Inc. PIC18FXX8 RETURN Syntax: Operands: Operation: Return from Subroutine [ label ] s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s RLCF Syntax: Operands: Rotate Left f through Carry [ label ] RLCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f 0011 01da ffff ffff RETURN [s] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2 No operation No operation The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, then the bank will be selected as per the BSR value (default). C register f Words: Cycles: Q Cycle Activity: Q1 Decode No operation Words: Q3 Process Data No operation 1 1 Q2 Read register 'f' RLCF Q4 pop PC from stack No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Example: Example: After Interrupt PC = TOS RETURN Before Instruction REG C REG W C = = = = = 1110 0110 0 1110 0110 1100 1100 1 After Instruction 2002 Microchip Technology Inc. DS41159B-page 309 PIC18FXX8 RLNCF Syntax: Operands: Rotate Left f (no carry) [ label ] RLNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f 0100 01da ffff ffff RRCF Syntax: Operands: Rotate Right f through Carry [ label ] RRCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f 0011 00da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are rotated one bit to the left. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). register f The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). C register f Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Words: Q2 Read register 'f' RLNCF 1 1 Q2 Read register 'f' RRCF Q3 Process Data REG Q4 Write to destination Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Example: REG REG = = Before Instruction 1010 1011 0101 0111 Example: REG C REG W C = = = = = After Instruction Before Instruction 1110 0110 0 1110 0110 0111 0011 0 After Instruction DS41159B-page 310 2002 Microchip Technology Inc. PIC18FXX8 RRNCF Syntax: Operands: Rotate Right f (no carry) [ label ] RRNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f 0100 00da ffff ffff SETF Syntax: Operands: Operation: Status Affected: Encoding: Description: Set f [ label ] SETF 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff f [,a] Operation: Status Affected: Encoding: Description: The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). register f The contents of the specified register are set to FFh. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' SETF Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register 'f' RRNCF Example: Q3 Process Data REG, 1, 0 Before Instruction Q4 Write to destination REG = = 0x5A 0xFF After Instruction REG Example 1: REG REG = = Before Instruction 1101 0111 1110 1011 RRNCF REG, W After Instruction Example 2: W REG W REG Before Instruction = = = = ? 1101 0111 1110 1011 1101 0111 After Instruction 2002 Microchip Technology Inc. DS41159B-page 311 PIC18FXX8 SLEEP Syntax: Operands: Operation: Enter SLEEP mode [ label ] SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 SUBFWB Syntax: Operands: Subtract f from W with borrow [ label ] SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z 0101 01da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 Q2 No operation SLEEP Words: Cycles: Q Cycle Activity: Q1 Decode Subtract register 'f' and carry flag (borrow) from W (2's complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' Words: Q3 Process Data Q4 Go to sleep Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Example: TO = PD = TO = PD = ? ? Before Instruction Example 1: REG W C REG W C Z N = = = = = = = = SUBFWB REG Before Instruction 0x03 0x02 0x01 0xFF 0x02 0x00 0x00 0x01 SUBFWB After Instruction 1 0 After Instruction If WDT causes wake-up, this bit is cleared. ; result is negative REG, 0, 0 Example 2: REG W C REG W C Z N = = = = = = = = Before Instruction 2 5 1 2 3 1 0 0 After Instruction ; result is positive REG, 1, 0 Example 3: REG W C REG W C Z N = = = = = = = = SUBFWB Before Instruction 1 2 0 0 2 1 1 0 After Instruction ; result is zero DS41159B-page 312 2002 Microchip Technology Inc. PIC18FXX8 SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z 0000 1000 kkkk kkkk SUBWF Syntax: Operands: Subtract W from f [ label ] SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z 0101 11da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: W is subtracted from the eight-bit literal 'k'. The result is placed in W. 1 1 Q2 Read literal 'k' SUBLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x02 Q4 Write to W Subtract W from register 'f' (2's complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' SUBWF Example 1: W C W C Z N = = = = = = Words: Cycles: Q Cycle Activity: Q1 Decode Before Instruction 1 ? 1 1 0 0 SUBLW After Instruction ; result is positive Q3 Process Data REG Q4 Write to destination Example 1: 0x02 Example 2: W C W C Z N = = = = = = Before Instruction REG W C REG W C Z N = = = = = = = = 3 2 ? 1 2 1 0 0 SUBWF Before Instruction 2 ? 0 1 1 0 SUBLW After Instruction After Instruction ; result is zero ; result is positive Example 3: W C W C Z N = = = = = = 0x02 Example 2: REG W C REG W C Z N = = = = = = = = REG, W Before Instruction 3 ? FF ; (2's complement) 0 ; result is negative 0 1 Before Instruction 2 2 ? 2 0 1 1 0 SUBWF After Instruction After Instruction ; result is zero Example 3: REG W C REG W C Z N = = = = = = = = REG Before Instruction 0x01 0x02 ? 0xFFh ;(2's complement) 0x02 0x00 ; result is negative 0x00 0x01 After Instruction 2002 Microchip Technology Inc. DS41159B-page 313 PIC18FXX8 SUBWFB Syntax: Operands: Subtract W from f with Borrow [ label ] SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z 0101 10da ffff ffff SWAPF Syntax: Operands: Swap f [ label ] SWAPF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: Subtract W and the carry flag (borrow) from register 'f' (2's complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' SUBWFB Words: Cycles: Q Cycle Activity: Q1 Decode The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' SWAPF Words: Cycles: Q3 Process Data REG, 1, 0 Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write to destination Example 1: REG W C REG W C Z N = = = = = = = = Before Instruction 0x19 0x0D 0x01 0x0C 0x0D 0x01 0x00 0x00 (0001 1001) (0000 1101) Example: REG REG = = Before Instruction 0x53 0x35 After Instruction (0000 1011) (0000 1101) After Instruction ; result is positive Example 2: REG W C REG W C Z N = = = = = = = = SUBWFB REG, 0, 0 Before Instruction 0x1B 0x1A 0x00 0x1B 0x00 0x01 0x01 0x00 SUBWFB (0001 1011) (0001 1010) After Instruction (0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1101) Example 3: REG W C REG W C Z N Before Instruction = = = = = = = = 0x03 0x0E 0x01 0xF5 0x0E 0x00 0x00 0x01 After Instruction (1111 0100) ; [2's comp] (0000 1101) ; result is negative DS41159B-page 314 2002 Microchip Technology Inc. PIC18FXX8 TBLRD Syntax: Operands: Operation: Table Read [ label ] None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* TBLRD Example1: Table Read (cont'd) TBLRD *+ ; TBLRD ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(0x00A356) = = = = = TBLRD +* ; 0x55 0x00A356 0x34 0x34 0x00A357 After Instruction TABLAT TBLPTR Example2: Before Instruction TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358) = = = = = = 0xAA 0x01A357 0x12 0x34 0x34 0x01A358 Status Affected:None Encoding: After Instruction TABLAT TBLPTR Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q2 No operation No operation (Read Program Memory) Words: Cycles: Q Cycle Activity: Q1 Decode No operation Q3 No operation Q4 No operation No No operation operation (Write TABLAT) 2002 Microchip Technology Inc. DS41159B-page 315 PIC18FXX8 TBLWT Syntax: Operands: Operation: Table Write [ label ] None if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Holding Register; 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* TBLWT Table Write (Continued) Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode No operation TBLWT ( *; *+; *-; +*) Q2 No operation No operation (Read TABLAT) Q3 No operation No operation Q4 No operation No operation (Write to Holding Register ) Example1: TBLWT *+; = = = = = = 0x55 0x00A356 0xFF 0x55 0x00A357 0x55 Status Affected: None Encoding: Before Instruction TABLAT TBLPTR HOLDING REGISTER (0x00A356) TABLAT TBLPTR HOLDING REGISTER (0x00A356) After Instructions (table write completion) Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 for additional details on programming FLASH memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Example 2: TBLWT +*; = = = = = = = = 0x34 0x01389A 0xFF 0xFF 0x34 0x01389B 0xFF 0x34 Before Instruction TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) After Instruction (table write completion) DS41159B-page 316 2002 Microchip Technology Inc. PIC18FXX8 TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, skip if 0 [ label ] TSTFSZ f [,a] 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k W N, Z 0000 1010 kkkk kkkk If 'f' = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of W are XORed with the 8-bit literal 'k'. The result is placed in W. 1 1 Q2 Read literal 'k' XORLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0xAF Q4 Write to W Words: Cycles: Example: W W = = Before Instruction 0xB5 0x1A Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation After Instruction If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NZERO ZERO Q4 No operation No operation No operation No operation TSTFSZ : : CNT Example: Before Instruction PC = = = = Address (HERE) 0x00, Address (ZERO) 0x00, Address (NZERO) After Instruction If CNT PC If CNT PC 2002 Microchip Technology Inc. DS41159B-page 317 PIC18FXX8 XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z 0001 10da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: Exclusive OR the contents of W with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in the register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' XORWF Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write to destination Example: REG W REG W = = = = Before Instruction 0xAF 0xB5 0x1A 0xB5 After Instruction DS41159B-page 318 2002 Microchip Technology Inc. PIC18FXX8 26.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board 26.2 MPASM Assembler The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process. 26.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help 26.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display. 2002 Microchip Technology Inc. Preliminary DS41159B-page 319 PIC18FXX8 26.4 MPLINK Object Linker/ MPLIB Object Librarian 26.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user. 26.7 ICEPIC In-Circuit Emulator 26.5 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool. The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present. DS41159B-page 320 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 26.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime. 26.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB. 26.9 PRO MATE II Universal Device Programmer The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode. 26.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad. 26.10 PICSTART Plus Entry Level Development Programmer The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2002 Microchip Technology Inc. Preliminary DS41159B-page 321 PIC18FXX8 26.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. 26.14 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 26.15 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters. DS41159B-page 322 Preliminary 2002 Microchip Technology Inc. 24CXX/ 25CXX/ 93CXX PIC14000 HCSXXX PIC16C5X PIC16C6X PIC16C7X PIC17C4X PIC16F62X PIC16C8X/ PIC16F8X PIC16C7XX PIC16F8XX PIC16C9XX PIC17C7XX PIC18CXX2 PIC12CXXX PIC16CXXX PIC18FXXX MCRFXXX MCP2510 TABLE 26-1: MPLAB(R) Integrated Development Environment 9 9 9 9 9 9 9 9 9 9 9 9 9 99 99 MPLAB(R) C17 C Compiler Software Tools MPLAB(R) C18 C Compiler MPASMTM Assembler/ MPLINKTM Object Linker 9 9 Programmers Debugger Emulators Demo Boards and Eval Kits 2002 Microchip Technology Inc. 999 999 99 ** 99 99 99 99 99 99 99 99 99 99 99 99 MPLAB(R) ICE In-Circuit Emulator ICEPICTM In-Circuit Emulator 9 * * 9 9 9 9 9 9 9 MPLAB(R) ICD In-Circuit Debugger 9 ** 9 9 9 PICSTART(R) Plus Entry Level Development Programmer 9 ** 9 9 9 9 9 9 9 9 9 9 9 9 9 9 PRO MATE(R) II Universal Device Programmer 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 DEVELOPMENT TOOLS FROM MICROCHIP Preliminary 9 9 9 9 9 PICDEMTM 1 Demonstration Board PICDEMTM 2 Demonstration Board 9 9 9 9 PICDEMTM 3 Demonstration Board 9 PICDEMTM 14A Demonstration Board 9 PICDEMTM 17 Demonstration Board 9 KEELOQ(R) Evaluation Kit 99 KEELOQ(R) Transponder Kit microIDTM Programmer's Kit 99 125 kHz microIDTM Developer's Kit 125 kHz Anticollision microIDTM Developer's Kit 9 13.56 MHz Anticollision microIDTM Developer's Kit 9 PIC18FXX8 DS41159B-page 323 MCP2510 CAN Developer's Kit * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices. 9 PIC18FXX8 NOTES: DS41159B-page 324 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports (combined) ....................................................................................................200 mA Maximum current sourced by all ports (combined) ...............................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. Preliminary DS41159B-page 325 PIC18FXX8 FIGURE 27-1: PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FXX8 4.2V Voltage 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 27-2: PIC18LFXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LFXX8 4.2V Voltage 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 40 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz, if VDDAPPMIN 4.2V = 40 MHz, if VDDAPPMIN > 4.2V Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. DS41159B-page 326 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 27.1 DC Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Supply Voltage PIC18LFXX8 PIC18FXX8 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage PIC18LFXX8 D005 BORV1:BORV0 = 11 BORV1:BORV0 = 10 BORV1:BORV0 = 01 BORV1:BORV0 = 00 PIC18FXX8 D005 BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00 N.A. 4.2 4.5 -- -- -- N.A. 4.46 4.78 V V V Not in operating voltage range of device 2.0 2.7 4.2 4.5 -- -- -- -- 2.16 2.86 4.46 4.78 V V V V 2.0 4.2 1.5 -- -- -- -- -- 5.5 5.5 -- 0.7 V V V V See section on Power-on Reset for details HS, XT, RC and LP osc mode Min Typ(5) Max Units Conditions PIC18LFXX8 (Industrial) PIC18FXX8 (Industrial, Extended) Param Symbol No. VDD D001 D001 D002 D003 D004 SVDD 0.05 -- -- V/ms See section on Power-on Reset for details VBOR Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Typical is taken at 25C. 2002 Microchip Technology Inc. Preliminary DS41159B-page 327 PIC18FXX8 27.1 DC Characteristics (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Supply Current(2,3,4) PIC18LFXX8 -- D010 D010A D010A D010C D010C D013 PIC18FXX8 -- PIC18LFXX8 -- PIC18FXX8 -- PIC18LFXX8 -- PIC18FXX8 -- PIC18LFXX8 -- -- -- D013 PIC18FXX8 -- -- D014 D014 PIC18LFXX8 -- PIC18FXX8 -- 62 TBD A 32 TBD A 14 22 TBD TBD mA mA 1.4 14 22 TBD TBD TBD mA mA mA 22 TBD mA 22 TBD mA 185 TBD A 30 TBD A 2 TBD mA 1 TBD mA XT, RC, RCIO osc configurations FOSC = 4 MHz, VDD = 2.0V XT, RC, RCIO osc configurations FOSC = 4 MHz, VDD = 4.2V LP osc configuration FOSC = 32 kHz, VDD = 2.0V LP osc configuration FOSC = 32 kHz, VDD = 4.2V EC, ECIO osc configurations, FOSC = 40 MHz, VDD = 5.5V EC, ECIO osc configurations, FOSC = 40 MHz, VDD = 5.5V HS osc configurations FOSC = 6 MHz, VDD = 2.5V FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configuration FOSC = 10 MHz, VDD = 5.5V HS osc configurations FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configuration FOSC = 10 MHz, VDD = 5.5V Timer1 osc configuration FOSC = 32 kHz, VDD = 2.5V OSCB osc configuration FOSC = 32 kHz, VDD = 4.2V Min Typ(5) Max Units Conditions PIC18LFXX8 (Industrial) PIC18FXX8 (Industrial, Extended) Param Symbol No. IDD D010 Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Typical is taken at 25C. DS41159B-page 328 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 27.1 DC Characteristics (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Power-down Current(3) PIC18LFXX8 PIC18FXX8 -- -- -- -- -- -- IWDT D022 D022 D022A IBOR D022A D022B ILVD D022B D025 D025 IOSCB Module Differential Current Watchdog Timer PIC18LFXX8 Watchdog Timer PIC18FXX8 Brown-out Reset PIC18LFXX8 Brown-out Reset PIC18FXX8 Low Voltage Detect PIC18LFXX8 Low Voltage Detect PIC18FXX8 Timer1 Oscillator PIC18LFXX8 Timer1 Oscillator PIC18FXX8 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 15 15 15 40 40 40 30 40 40 8 9 9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A A A A A A A A A A A A A VDD = 2.5V VDD = 5.5V VDD = 5.5V, -40C to +85C VDD = 5.5V, -40C to +125C VDD = 5.5V VDD = 5.5V, -40C to +85C VDD = 5.5V, -40C to +125 VDD = 2.5V VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C VDD = 2.5V VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C 0.09 TBD 0.11 TBD 0.1 0.11 0.1 0.11 TBD TBD TBD TBD A A A A A A VDD = 2.5V, -40C to +85C VDD = 5.5V, -40C to +85C VDD = 4.2V, -40C to +85C VDD = 5.5V, -40C to +85C VDD = 4.2V, -40C to +125C VDD = 5.5V, -40C to +125C Min Typ(5) Max Units Conditions PIC18LFXX8 (Industrial) PIC18FXX8 (Industrial, Extended) Param Symbol No. IPD D020 D020 D021B Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Typical is taken at 25C. 2002 Microchip Technology Inc. Preliminary DS41159B-page 329 PIC18FXX8 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Input Low Voltage I/O ports: D030 D030A D031 D032 D032A D033 VIH D040 D040A D041 D042 D042A D043 D050 VHYS IIL D060 D061 D063 IPU D070 IPURB with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 (in XT, HS and LP modes) and T1OSI OSC1 (RC mode)(1) Hysteresis of Schmitt Trigger Inputs Input Leakage Current(2,3) I/O ports MCLR OSC1 Weak Pull-up Current PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS -- -- -- 1 5 5 A A A VSS VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 (in XT, HS and LP modes) and T1OSI OSC1 (in RC mode)(1) Input High Voltage I/O ports: with TTL buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.7 VDD 0.8 VDD 0.7 VDD 0.9 VDD TBD VDD VDD VDD VDD VDD VDD VDD TBD V V V V V V V V VDD < 4.5V 4.5V VDD 5.5V with TTL buffer VSS -- VSS VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.3 VDD 0.2 VDD V V V V V V V VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS41159B-page 330 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Max Units Conditions DC CHARACTERISTICS Param Symbol No. VOL D080 D080A D083 D083A VOH D090 D090A D092 D092A D150 VOD Open Drain High Voltage Capacitive Loading Specs on Output Pins D101 D102 CIO CB All I/O pins and OSC2 (in RC mode) SCL, SDA OSC2/CLKO (RC mode) Output High Voltage(3) I/O ports OSC2/CLKO (RC mode) Characteristic/ Device Output Low Voltage I/O ports -- -- -- -- 0.6 0.6 0.6 0.6 V V V V IOL = 8.5 mA, VDD = 4.2V, -40C to +85C IOL = 7.0 mA, VDD = 4.2V, -40C to +125C IOL = 1.6 mA, VDD = 4.2V, -40C to +85C IOL = 1.2 mA, VDD = 4.2V, -40C to +125C IOH = -3.0 mA, VDD = 4.2V, -40C to +85C IOH = -2.5 mA, VDD = 4.2V, -40C to +125C IOH = -1.3 mA, VDD = 4.2V, -40C to +85C IOH = -1.0 mA, VDD = 4.2V, -40C to +125C RA4 pin VDD - 0.7 VDD - 0.7 VDD - 0.7 VDD - 0.7 -- -- -- -- -- 7.5 V V V V V -- -- 50 400 pF pF To meet the AC Timing Specifications In I2C mode Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2002 Microchip Technology Inc. Preliminary DS41159B-page 331 PIC18FXX8 FIGURE 27-3: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) 37 LVDIF TABLE 27-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param Symbol No. D420 VLVD LVD Voltage Characteristic LVDL<3:0> = 0000 LVDL<3:0> = 0001 LVDL<3:0> = 0010 LVDL<3:0> = 0011 LVDL<3:0> = 0100 LVDL<3:0> = 0101 LVDL<3:0> = 0110 LVDL<3:0> = 0111 LVDL<3:0> = 1000 LVDL<3:0> = 1001 LVDL<3:0> = 1010 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110 Min -- 2.0 2.2 2.4 2.5 2.7 2.8 3.0 3.3 3.5 3.6 3.8 4.0 4.2 4.5 1.17 Max -- 2.12 2.33 2.54 2.66 2.86 2.98 3.2 3.52 3.72 3.84 4.04 4.26 4.46 4.78 1.23 Units V V V V V V V V V V V V V V V V Conditions (Note 1) D423 VBGAP Bandgap Reference Voltage Value Note 1: This is not a valid setting since the minimum supply voltage is 2.0V. DS41159B-page 332 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 TABLE 27-2: DC CHARACTERISTICS: EEPROM AND ENHANCED FLASH Standard Operating Conditions Characteristic Data EEPROM Memory D120 D120A D121 D122 D123 D124 ED ED VDRW Byte Endurance Byte Endurance VDD for Read/Write 100K 10K VMIN -- 40 1M 1M 100K -- 2 -- 10M -- -- 5.5 -- -- -- E/W E/W V -40C to +85C +85C to +125C Using EECON to read/write VMIN = Minimum operating voltage Min Typ Max Units Conditions DC Characteristics Param No. Sym TDEW Erase/Write Cycle Time TRETD Retention TREF Number of Total Erase/Write Cycles to Data EEPROM before Refresh* Number of Total Erase/Write Cycles to Data EEPROM before Refresh* Program Flash Memory Cell Endurance Cell Endurance VDD for Read VDD for ISCP Erase VDD for ISCP Write VDD for EECON Erase/Write ms Years Provided no specifications are violated Cycles -40C to +85C D124A TREF 100K 1M -- Cycles +85C to +125C D130 D130A D131 D132 D132A D132B D133 D133A D133B D134 * EP EP VPR VIE VIW VPEW TIE TIW 10K 1000 VMIN 4.5 4.5 VMIN -- 1 -- 40 100K 10K -- -- -- -- 4 -- 2 -- -- -- 5.5 5.5 5.5 5.5 -- -- -- -- E/W E/W V V V V ms ms ms Years Provided no specifications are violated Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. See Section 5.8 for more information. ICSP Erase Cycle Time ICSP Erase or Write Cycle Time (externally timed) TPIW Self-timed Write Cycle Time TRETD Retention -40C to +85C +85C to +125C VMIN = Minimum operating voltage Using ICSP port Using ICSP port Using EECON to erase/write VMIN = Minimum operating voltage VDD > 4.5V VDD > 4.5V 2002 Microchip Technology Inc. Preliminary DS41159B-page 333 PIC18FXX8 TABLE 27-3: COMPARATOR SPECIFICATIONS Operating Conditions: VDD range as described in Section 27.1, -40C < TA < +125C. Param No. D300 D301 D302 D300 D301 Sym VIOFF VICM CMRR TRESP Characteristics Input Offset Voltage Input Common Mode Voltage CMRR Response Time(1) 0 +55* TBD* TBD* TBD* TBD* 10* Min Typ 5.0 Max 10 VDD - 1.5 Units mV V db ns ns s PIC18FXX8 PIC18LFXX8 Comments TMC2OV Comparator Mode Change to Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD. TABLE 27-4: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: VDD range as described in Section 27.1, -40C < TA < +125C. Param No. D310 D311 D312 D310 Sym VRES VRAA VRUR TSET Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) 2K* 10* Min VDD/24 Typ Max VDD/32 TBD Units LSB LSB s Comments * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. DS41159B-page 334 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 27.3 27.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F H I L I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD ST DAT STA DATA input hold START condition STO STOP condition Hold SU Setup High Low High Low Fall High Invalid (Hi-impedance) Low P R V Z Period Rise Valid Hi-impedance osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) 2002 Microchip Technology Inc. Preliminary DS41159B-page 335 PIC18FXX8 27.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications, unless otherwise noted. Figure 27-4 specifies the load conditions for the timing specifications. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 27.1. LC parts operate for industrial temperatures only. AC CHARACTERISTICS FIGURE 27-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load Condition 2 RL Pin DS41159B-page 336 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 27.3.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 FIGURE 27-5: OSC1 1 2 3 3 4 4 CLKO TABLE 27-6: Param No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol Characteristic External CLKI Frequency(1) Min DC DC 4 DC DC Oscillator Frequency(1) DC 0.1 4 4 5 Max 4 25 10 200 40 4 4 25 10 200 -- -- -- -- -- -- 10,000 10,000 100 -- -- -- -- -- 20 50 7.5 Units MHz XT osc MHz HS osc MHz HS + PLL osc kHz LP osc MHz EC MHz RC osc MHz XT osc MHz HS osc MHz HS + PLL osc kHz ns ns ns s ns ns ns ns ns s ns ns ns s ns ns ns LP osc XT and RC osc HS osc HS + PLL osc LP osc EC RC osc XT osc HS osc HS + PLL osc LP osc TCY = 4/FOSC XT osc LP osc HS osc XT osc LP osc HS osc Conditions FOSC 1 TOSC External CLKI Period(1) 250 40 100 5 5 Oscillator Period(1) 250 250 100 40 5 2 3 TCY TosL, TosH Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time 100 30 2.5 10 -- -- -- 4 TosR, TosF External Clock in (OSC1) Rise or Fall Time Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 2002 Microchip Technology Inc. Preliminary DS41159B-page 337 PIC18FXX8 TABLE 27-7: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V) Characteristic PLL Start-up Time (Lock Time) CLKO Stability (Jitter) using PLL Min -- TBD Max 2 TBD Units ms % Conditions Param No. Symbol 7 TPLL CLK FIGURE 27-6: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 CLKO 13 14 I/O Pin (Input) 17 I/O Pin (Output) Old Value 20, 21 Note: Refer to Figure 27-4 for load conditions. 15 New Value 19 18 12 16 11 TABLE 27-8: Param No. 10 11 12 13 14 15 16 17 18 18A 19 20 20A 21 21A 22 23 24 TINP TRBP TRCP TIOF TIOR CLKO AND I/O TIMING REQUIREMENTS Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 -- -- -- -- TCY TCY 20 Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- -- Max 200 200 100 100 0.5 TCY + 20 -- -- 150 -- -- -- 25 60 25 60 -- -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) (1) (1) (1) (1) (1) Symbol TosH2ckL OSC1 to CLKO TosH2ckH OSC1 to CLKO TckR TckF CLKO rise time CLKO fall time TckL2ioV CLKO to Port out valid TioV2ckH Port in valid before CLKO TckH2ioI TosH2ioI Port in hold after CLKO OSC1 (Q2 cycle) to Port PIC18FXX8 input invalid (I/O in hold time) PIC18LFXX8 Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time RC7:RC4 change INT high or low time PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 TosH2ioV OSC1 (Q1 cycle) to Port out valid TioV2osH Port input valid to OSC1 (I/O in setup time) These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC. DS41159B-page 338 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 27-4 for load conditions. 32 30 31 34 FIGURE 27-8: BROWN-OUT RESET AND LOW VOLTAGE DETECT TIMING BVDD (for 35) VLVD (for 37) 35, 37 VBGAP = 1.2V VDD VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable 36 TABLE 27-9: Param No. 30 31 32 33 34 35 36 37 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW VOLTAGE DETECT REQUIREMENTS Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become stable Low Voltage Detect Pulse Width Min 2 7 1024 TOSC 28 -- 200 -- 200 Typ -- 18 -- 72 2 -- 20 -- Max -- 33 1024 TOSC 132 -- -- 50 -- Units s Symbol TmcL TWDT TOST TPWRT TIOZ TBOR TIVRST TLVD Conditions ms -- ms s s s s TOSC = OSC1 period For VDD BVDD (see D005) For VDD VLVD (see D420) 2002 Microchip Technology Inc. Preliminary DS41159B-page 339 PIC18FXX8 FIGURE 27-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 TMR0 or TMR1 Note: Refer to Figure 27-4 for load conditions. 48 TABLE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. 40 41 42 Tt0H Tt0L Tt0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or TCY + 40 N 0.5 TCY + 20 10 25 30 50 0.5 TCY + 5 10 25 30 TBD Greater of: 20 ns or TCY + 40 N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions 45 Tt1H T1CKI High Time Synchronous, no prescaler Synchronous, PIC18FXX8 with prescaler PIC18LFXX8 Asynchronous PIC18FXX8 PIC18LFXX8 -- -- -- -- -- -- -- -- -- TBD -- ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8) 46 Tt1L T1CKI Low Time Synchronous, no prescaler Synchronous, PIC18FXX8 with prescaler PIC18LFXX8 Asynchronous PIC18FXX8 PIC18LFXX8 47 Tt1P T1CKI Synchronous Input Period Asynchronous -- 50 7 TOSC ns kHz -- Ft1 48 T1CKI Oscillator Input Frequency Range Tcke2tmrI Delay from External T1CKI Clock Edge to Timer Increment DS41159B-page 340 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND ECCP1) CCPx (Capture Mode) 50 52 51 CCPx (Compare or PWM Mode) 53 Note: Refer to Figure 27-4 for load conditions. 54 TABLE 27-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND ECCP1) Param Symbol No. 50 TccL Characteristic CCPx input low No Prescaler time With PIC18FXX8 Prescaler PIC18LFXX8 CCPx input high time No Prescaler With Prescaler PIC18FXX8 PIC18LFXX8 Min 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N PIC18FXX8 PIC18LFXX8 54 TccF CCPx output fall time PIC18FXX8 PIC18LFXX8 -- -- -- -- Max -- -- -- -- -- -- -- 25 45 25 45 Units ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions 51 TccH 52 53 TccP TccR CCPx input period CCPx output fall time 2002 Microchip Technology Inc. Preliminary DS41159B-page 341 PIC18FXX8 FIGURE 27-11: RE2/CS PARALLEL SLAVE PORT TIMING (PIC18F248 AND PIC18F458) RE0/RD RE1/WR 65 RD7:RD0 62 63 Note: Refer to Figure 27-4 for load conditions. 64 TABLE 27-12: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F248 AND PIC18F458) Param No. 62 63 64 65 66 Symbol TdtV2wrH TwrH2dtI TrdL2dtV TrdH2dtI TibfINH Characteristic Data-in valid before WR or CS (setup time) WR or CS to data-in invalid (hold time) RD and CS to data-out valid RD or CS to data-out invalid Inhibit the IBF flag bit being cleared from WR or CS PIC18FXX8 PIC18LFXX8 Min 20 25 20 35 -- -- 10 -- Max -- -- -- -- 80 90 30 3 TCY Units ns ns ns ns ns ns ns ns Extended Temp. range Conditions Extended Temp. range DS41159B-page 342 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-12: SS 70 SCK (CKP = 0) 71 72 78 SCK (CKP = 1) 79 78 79 EXAMPLE SPI MASTER MODE TIMING (CKE = 0) 80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 27-4 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1 LSb LSb In TABLE 27-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. 70 71 71A 72 72A 73 73A 74 75 76 78 79 80 TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR TscF TscH2doV, TscL2doV TscL Symbol TssL2scH, TssL2scL TscH Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Continuous Single Byte Continuous Single Byte Min TCY 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- -- PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 -- -- -- -- -- Max Units -- -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18FXX8 PIC18LFXX8 SCK output fall time (Master mode) SDO data output valid after SCK edge Note 1: Requires the use of parameter # 73A. 2: Only if parameter #'s 71A and 72A are used. 2002 Microchip Technology Inc. Preliminary DS41159B-page 343 PIC18FXX8 FIGURE 27-13: SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79 EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SDO MSb 75, 76 Bit6 - - - - - -1 LSb SDI MSb In 74 Bit6 - - - -1 LSb In Note: Refer to Figure 27-4 for load conditions. TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param No. 71 71A 72 72A 73 73A 74 75 76 78 79 80 81 TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR TscF TscH2doV, TscL2doV TscL Symbol TscH Characteristic SCK input high time (Slave mode) SCK input low time (Slave mode) Continuous Single Byte Continuous Single Byte Min 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- -- PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 -- -- -- -- -- TCY Max Units -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18FXX8 PIC18LFXX8 SCK output fall time (Master mode) SDO data output valid after SCK edge TdoV2scH, SDO data output setup to SCK edge TdoV2scL Note 1: Requires the use of parameter # 73A. 2: Only if parameter #'s 71A and 72A are used. DS41159B-page 344 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-14: SS 70 SCK (CKP = 0) 71 72 83 EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) 78 79 SCK (CKP = 1) 80 SDO MSb 75, 76 SDI 73 MSb In 74 Bit6 - - - -1 LSb In Bit6 - - - - - -1 79 78 LSb 77 Note: Refer to Figure 27-4 for load conditions. TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0) Param No. 70 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83 TscL SCK input low time (Slave mode) Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) PIC18FXX8 PIC18LFXX8 SCK output fall time (Master mode) PIC18FXX8 PIC18LFXX8 1.5 TCY + 40 -- -- TscH2doV, SDO data output valid after SCK TscL2doV edge TscH2ssH, SS after SCK edge TscL2ssH PIC18FXX8 PIC18LFXX8 -- 10 -- 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- Max Units Conditions -- -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time (Slave mode) Note 1: Requires the use of parameter # 73A. 2: Only if parameter #'s 71A and 72A are used. 2002 Microchip Technology Inc. Preliminary DS41159B-page 345 PIC18FXX8 FIGURE 27-15: SS EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb 75, 76 Bit6 - - - - - -1 LSb 77 SDI MSb In Bit6 - - - -1 LSb In 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. 70 71 71A 72 72A 73A 74 75 76 77 78 79 80 82 83 Symbol TssL2scH, TssL2scL TscH TscL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TssL2doV Characteristic SS to SCK or SCK input SCK input high time (Slave mode) Min TCY Max Units Conditions -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Continuous 1.25 TCY + 30 Single Byte 40 SCK input low time Continuous 1.25 TCY + 30 (Slave mode) Single Byte 40 Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 Hold time of SDI data input to SCK edge 100 SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 -- -- -- 10 -- -- -- -- -- -- -- 1.5 TCY + 40 (Note 1) (Note 1) (Note 2) SCK output fall time (Master mode) SDO data output valid after SCK PIC18FXX8 edge PIC18LFXX8 SDO data output valid after SS edge PIC18FXX8 PIC18LFXX8 TscH2ssH, SS after SCK edge TscL2ssH Note 1: Requires the use of parameter # 73A. 2: Only if parameter #'s 71A and 72A are used. DS41159B-page 346 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-16: I2C BUS START/STOP BITS TIMING SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 27-4 for load conditions. STOP Condition TABLE 27-17: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param No. 90 91 92 93 Symbol TSU:STA THD:STA TSU:STO Characteristic START condition Setup time START condition Hold time STOP condition Setup time THD:STO STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated FIGURE 27-17: I2C BUS DATA TIMING 103 100 101 102 SCL 90 91 106 107 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 27-4 for load conditions. 2002 Microchip Technology Inc. Preliminary DS41159B-page 347 PIC18FXX8 TABLE 27-18: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param No. 100 Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101 TLOW Clock low time 100 kHz mode 400 kHz mode SSP module 102 TR SDA and SCL rise time SDA and SCL fall time START condition setup time START condition hold time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode D102 CB Bus capacitive loading Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 s s ns ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 to 400 pF Only relevant for Repeated START condition After this period the first clock pulse is generated CB is specified to be from 10 to 400 pF PIC18FXX8 must operate at a minimum of 1.5 MHz PIC18FXX8 must operate at a minimum of 10 MHz Units s s Conditions PIC18FXX8 must operate at a minimum of 1.5 MHz PIC18FXX8 must operate at a minimum of 10 MHz 103 TF 90 91 106 107 92 109 110 TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + TSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification). DS41159B-page 348 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 27-4 for load conditions. STOP Condition TABLE 27-19: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param Symbol No. 90 TSU:STA Characteristic START condition Setup time 91 THD:STA START condition Hold time 92 TSU:STO STOP condition Setup time 93 THD:STO STOP condition Hold time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) Note 1: Maximum pin capacitance = 10 pF for all I2C Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) pins. Max -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated FIGURE 27-19: MASTER SSP I2C BUS DATA TIMING 103 100 101 102 SCL SDA In 90 91 106 107 92 109 109 110 SDA Out Note: Refer to Figure 27-4 for load conditions. 2002 Microchip Technology Inc. Preliminary DS41159B-page 349 PIC18FXX8 TABLE 27-20: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol No. 100 THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode 1 MHz mode(1) 101 TLOW Clock low time 100 kHz mode 400 kHz mode 1 MHz 102 TR SDA and SCL rise time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 103 TF SDA and SCL fall time 100 kHz mode 400 kHz mode 1 MHz mode(1) 90 TSU:STA START condition 100 kHz mode setup time 400 kHz mode 1 MHz mode(1) 91 THD:STA START condition 100 kHz mode hold time 400 kHz mode 1 MHz mode(1) 106 THD:DAT Data input hold time 100 kHz mode 400 kHz mode 1 MHz mode(1) 107 TSU:DAT Data input setup time 100 kHz mode 400 kHz mode 1 MHz mode(1) 92 TSU:STO STOP condition setup time 100 kHz mode 400 kHz mode 1 MHz mode(1) 109 TAA Output valid from 100 kHz mode clock 400 kHz mode 1 MHz 110 TBUF Bus free time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) D102 CB Bus capacitive loading Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 TBD 250 100 TBD 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 TBD -- Max -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 Units ms ms ms ms ms ms ns ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ns ns ms ms ms ns ns ns ms ms ms pF Time the bus must be free before a new transmission can start (Note 2) Only relevant for Repeated START condition After this period, the first clock pulse is generated CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Conditions Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode). DS41159B-page 350 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 120 121 121 122 Note: Refer to Figure 27-4 for load conditions. TABLE 27-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 Symbol Characteristic Min Max Units Conditions TckH2dtV SYNC XMIT (Master & Slave) Clock high to data-out valid Tckrf Tdtrf Clock out rise time and fall time (Master mode) Data-out rise time and fall time PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 -- -- -- -- -- -- 40 100 20 50 20 50 ns ns ns ns ns ns 121 122 FIGURE 27-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 27-4 for load conditions. TABLE 27-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. 125 126 Symbol TdtV2ckl TckL2dtl Characteristic SYNC RCV (Master & Slave) Data-hold before CK (DT hold time) Data-hold after CK (DT hold time) Min Max Units Conditions 10 15 -- -- ns ns 2002 Microchip Technology Inc. Preliminary DS41159B-page 351 PIC18FXX8 TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED) PIC18LFXX8 (INDUSTRIAL) Param Symbol No. A01 A03 A04 A05 A06 A10 A20 A20A A21 A22 A25 A30 A40 VREFH VREFL VAIN ZAIN IAD NR EIL EDL EFS EOFF -- VREF Characteristic Resolution Integral linearity error Differential linearity error Full scale error Offset error Monotonicity Reference voltage (VREFH - VREFL) Reference voltage High Reference voltage Low Analog input voltage Recommended impedance of analog voltage source A/D conversion PIC18FXX8 current (VDD) PIC18LFXX8 VREF input current (Note 2) 0V 3V VSS VSS - 0.3V VSS - 0.3V -- -- -- 10 Min -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- guaranteed(3) -- -- -- -- -- -- 180 90 -- -- -- VDD + 0.3V VDD VREF + 0.3V 10.0 -- -- 1000 Max 10 TBD <1 TBD <1 TBD <1 TBD <1.5 TBD Units bit bit Conditions VREF = VDD 3.0V VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V -- V V V V V k A A A Average current consumption when A/D is on (Note 1). During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD. During A/D conversion cycle. For 10-bit resolution VSS VAIN VREF A50 IREF -- -- 10 A Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or VDD and VSS pins, whichever is selected as reference input. 2: VSS VAIN VREF 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS41159B-page 352 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 FIGURE 27-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) Q4 130 A/D CLK 132 131 A/D DATA 9 8 7 ... ... 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO SAMPLING STOPPED DONE TCY SAMPLE Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 27-24: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D clock period PIC18FXX8 PIC18LFXX8 PIC18FXX8 PIC18LFXX8 131 132 135 136 TCNV TACQ TSWC TAMP Conversion time (not including acquisition time) (Note 1) Acquisition time (Note 3) Switching time from convert sample Amplifier settling time (Note 2) Min 1.6 3.0 2.0 3.0 11 15 10 -- 1 Max 20(5) 20(5) 6.0 9.0 12 -- -- (Note 4) -- s This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Units s s s s TAD s s -40C Temp +125C 0C Temp +125C Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC mode A/D RC mode Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 20.0 for minimum conditions when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2002 Microchip Technology Inc. Preliminary DS41159B-page 353 PIC18FXX8 NOTES: DS41159B-page 354 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. 2002 Microchip Technology Inc. Preliminary DS41159B-page 355 PIC18FXX8 NOTES: DS41159B-page 356 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 29.0 29.1 PACKAGING INFORMATION Package Marking Information 28-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F258-I/SP 0220017 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F448-I/P 0220017 28-Lead SOIC XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F248-E/SO 0220017 Legend: XX...X Y YY WW NNN Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. Preliminary DS41159B-page 357 PIC18FXX8 29.1 Package Marking Information (Continued) 44-Lead PLCC Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F458 -I/L 0220017 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F448 -I/PT 0220017 DS41159B-page 358 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 29.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L A1 B1 B p c eB Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB INCHES* MIN NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX * Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 2002 Microchip Technology Inc. Preliminary DS41159B-page 359 PIC18FXX8 40-Lead Plastic Dual In-line (P) - 600 mil (PDIP) E1 D n E 2 1 A c A2 L A1 eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 5 10 15 Mold Draft Angle Top Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15 DS41159B-page 360 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC) E E1 p D B n h 45 c A 2 1 A2 L Units Dimension Limits n p A A2 A1 E E1 D h L c B A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0 .104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15 2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 2002 Microchip Technology Inc. Preliminary DS41159B-page 361 PIC18FXX8 44-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC) E E1 #leads=n1 D1 D n12 CH2 x 45 CH1 x 45 A3 A2 35 A B1 B p D2 c A1 E2 Units Dimension Limits n p INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5 MAX MIN Number of Pins Pitch Pins per Side n1 Overall Height A .180 Molded Package Thickness .160 A2 Standoff A1 .035 A3 Side 1 Chamfer Height .034 Corner Chamfer 1 CH1 .050 Corner Chamfer (others) CH2 .010 Overall Width E .695 Overall Length D .695 Molded Package Width E1 .656 Molded Package Length D1 .656 Footprint Width E2 .630 Footprint Length .630 D2 c Lead Thickness .013 Upper Lead Width B1 .032 B .021 Lower Lead Width 10 Mold Draft Angle Top Mold Draft Angle Bottom 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.59 14.99 15.75 14.99 15.75 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 MAX 4.57 4.06 0.89 0.86 1.27 0.25 17.65 17.65 16.66 16.66 16.00 16.00 0.33 0.81 0.53 10 10 DS41159B-page 362 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D B n 2 1 CH x 45 A c L A1 (F) A2 Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH MIN .039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5 INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MAX MIN .047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 MAX 1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 2002 Microchip Technology Inc. Preliminary DS41159B-page 363 PIC18FXX8 NOTES: DS41159B-page 364 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (June 2001) Original data sheet for the PIC18FXX8 family. The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (May 2002) Updated information on CAN module, device memory and register maps, I/O ports and Enhanced CCP. TABLE B-1: DEVICE DIFFERENCES Features PIC18F248 16K 8192 768 Ports A, B, C -- No 5 input channels No N/A 28-pin SPDIP 28-pin SOIC PIC18F258 32K 16384 1536 Ports A, B, C -- No 5 input channels No N/A 28-pin SPDIP 28-pin SOIC PIC18F448 16K 8192 768 1 Yes 8 input channels 2 Yes 40-pin PDIP 44-pin PLCC 44-pin TQFP PIC18F458 32K 16384 1536 1 Yes 8 input channels 2 Yes 40-pin PDIP 44-pin PLCC 44-pin TQFP Internal Program Memory Bytes # of Single word Instructions Data Memory (Bytes) I/O Ports Enhanced Capture/Compare/PWM Modules Parallel Slave Port 10-bit Analog-to-Digital Converter Analog Comparators Analog Comparators VREF Output Packages Ports A, B, C, D, E Ports A, B, C, D, E 2002 Microchip Technology Inc. Preliminary DS41159B-page 365 PIC18FXX8 APPENDIX C: DEVICE MIGRATIONS APPENDIX D: This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC18FXX8 family of devices. D.1 PIC16CXXX to PIC18FXX8 See Application Note AN716. D.2 PIC17CXXX to PIC18FXX8 See Application Note AN726. DS41159B-page 366 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 APPENDIX E: DEVELOPMENT TOOL VERSION REQUIREMENTS This lists the minimum requirements (software/ firmware) of the specified development tool to support the devices listed in this data sheet. MPLAB(R) SIMULATOR: MPLAB(R) ICE 2000: MPLAB IDE TBD PIC18FXX8 Processor Module: Part Number PCM 18XD0 PIC18FXX8 Device Adapter: Socket Part Number 28-pin PDIP 28-pin SOIC DVA16XP282 DVA16XP282 with XLT 28SO Transition Socket DVA16XP401 DVA16PQ441 with XLT 44PT Transition Socket DVA16XL441 TBD TBD V7.40 (MPLAB IDE V5.40) 40-pin PDIP 44-pin TQFP 44-pin PLCC MPLAB(R) ICD 2: PRO MATE II: Device Programmer (R) version TBD PICSTART(R) Plus: Development Programmer MPASMTM Assembler: V2.80 (MPLAB IDE V5.40) Not available at time of printing. OSEK/VDX operating system available from Vector Infromatik GmbH, Germany and Realogy Ltd, UK. MPLAB(R) C18 C Compiler: version TBD CAN-TOOL: Third Party Tools: Note: Please read all associated README.TXT files that are supplied with the development tools. These "read me" files will discuss product support and any known limitations. 2002 Microchip Technology Inc. Preliminary DS41159B-page 367 PIC18FXX8 NOTES: DS41159B-page 368 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 INDEX A A/D ................................................................................... 237 A/D Converter Flag (ADIF bit) .................................. 239 A/D Converter Interrupt, Configuring ....................... 240 Acquisition Requirements ........................................ 240 Acquisition Time ....................................................... 241 ADCON0 Register .................................................... 237 ADCON1 Register .................................................... 237 ADRESH Register .................................................... 237 ADRESH/ADRESL Registers .................................. 239 ADRESL Register .................................................... 237 Analog Port Pins, Configuring .................................. 242 Associated Registers Summary ............................... 243 Calculating the Minimum Required Acquisition Time ............................................... 241 Configuring the Module ............................................ 240 Conversion Clock (TAD) ........................................... 242 Conversion Status (GO/DONE bit) .......................... 239 Conversion TAD Cycles ............................................ 243 Conversions ............................................................. 243 Converter Characteristics ........................................ 352 Minimum Charging Time .......................................... 241 Selecting the Conversion Clock ............................... 242 Special Event Trigger (CCP) .................................... 124 Special Event Trigger (ECCP) ......................... 131, 243 TAD vs. Device Operating Frequencies (For Extended, LC Devices) (table) ................. 242 TAD vs. Device Operating Frequencies (table) ........ 242 Use of the ECCP Trigger ......................................... 243 Absolute Maximum Ratings ............................................. 325 AC (Timing) Characteristics ............................................. 335 Parameter Symbology ............................................. 335 Access Bank ...................................................................... 54 ACKSTAT ......................................................................... 171 ADCON0 Register ............................................................ 237 GO/DONE bit ........................................................... 239 ADCON1 Register ............................................................ 237 ADDLW ............................................................................ 283 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART ADDWF ............................................................................ 283 ADDWFC ......................................................................... 284 ADRESH Register ............................................................ 237 ADRESH/ADRESL Registers ........................................... 239 ADRESL Register ............................................................ 237 Analog-to-Digital Converter. See A/D ANDLW ............................................................................ 284 ANDWF ............................................................................ 285 Assembler MPASM Assembler .................................................. 319 Associated Registers ............................................... 190, 195 Block Diagrams A/D ........................................................................... 239 Analog Input Model ...........................................240, 249 Baud Rate Generator .............................................. 167 CAN Buffers and Protocol Engine ........................... 198 Capture Mode (CCP Module) .................................. 123 Comparator I/O Operating Modes ........................... 246 Comparator Output .................................................. 248 Compare (CCP Module) Mode Operation ............... 124 Enhanced PWM ....................................................... 132 Interrupt Logic ............................................................ 78 Low Voltage Detect ................................................. 256 Low Voltage Detect with External Input ................... 256 MSSP (I2C Master Mode) ........................................ 165 MSSP (I2C Mode) .................................................... 150 MSSP (SPI Mode) ................................................... 141 On-Chip Reset Circuit ................................................ 25 PIC18F248/258 Architecture ....................................... 8 PIC18F448/458 Architecture ....................................... 9 PLL ............................................................................ 19 PORTC (Peripheral Output Override) ........................ 98 PORTD and PORTE (Parallel Slave Port) ............... 105 PORTD in I/O Port Mode ......................................... 100 PORTE .................................................................... 102 PWM (CCP Module) ................................................ 126 RA3:RA0 and RA5 Port Pins ..................................... 93 RA4/T0CKI Pin .......................................................... 93 RA6/OSC2/CLKO Pin ................................................ 94 RB1:RB0 Port Pins .................................................... 95 RB2:CANTX Port Pins ............................................... 96 RB3:CANRX Port Pins ............................................... 96 RB7:RB4 Port Pins .................................................... 95 Reads from FLASH Program Memory ....................... 69 Receive Buffer ......................................................... 226 Table Read Operation ............................................... 65 Table Write Operation ................................................ 66 Table Writes to FLASH Program Memory ................. 71 Timer0 Module 16-bit Mode ...................................................... 108 8-bit Mode ........................................................ 108 Timer1 Module ......................................................... 112 Timer1 Module (16-bit Read/Write Mode) ............... 112 Timer2 ..................................................................... 116 Timer3 ..................................................................... 118 Timer3 (16-bit Read/Write Mode) ............................ 118 Transmit Buffer ........................................................ 223 USART Receive ....................................................... 189 USART Transmit ...................................................... 187 Voltage Reference ................................................... 252 Watchdog Timer ...................................................... 269 BN .................................................................................... 286 BNC ................................................................................. 287 BNN ................................................................................. 287 BNOV ............................................................................... 288 BNZ .................................................................................. 288 BOR. See Brown-out Reset BOV ................................................................................. 291 BRA ................................................................................. 289 B Bank Select Register (BSR) ............................................... 54 Baud Rate Generator ....................................................... 167 BC .................................................................................... 285 BCF .................................................................................. 286 BF ..................................................................................... 171 Bit Timing Configuration Registers BRGCON1 ............................................................... 232 BRGCON2 ............................................................... 232 BRGCON3 ............................................................... 232 2002 Microchip Technology Inc. Preliminary DS41159B-page 369 PIC18FXX8 BRG. See Baud Rate Generator Brown-out Reset (BOR) ............................................. 26, 261 BSF .................................................................................. 289 BTFSC ............................................................................. 290 BTFSS .............................................................................. 290 BTG .................................................................................. 291 BZ ..................................................................................... 292 Programming Time Segments ................................. 232 Propagation Segment .............................................. 230 Receive Buffer Registers ......................................... 208 Receive Buffers ....................................................... 226 Receive Message Buffering ..................................... 226 Receive Priority ........................................................ 226 Registers .................................................................. 199 Resynchronization ................................................... 231 Sample Point ........................................................... 230 Shortening a bit Period ............................................ 232 Stuff Bit Error ........................................................... 233 Synchronization ....................................................... 231 Synchronization Rules ............................................. 231 Synchronization Segment ........................................ 230 Time Quanta ............................................................ 230 Transmit Buffer Registers ........................................ 204 Transmit Buffers ...................................................... 223 Transmit Message Flow Chart ................................. 225 Transmit Priority ....................................................... 223 Transmit/Receive Buffers ........................................ 197 Values for ICODE (table) ......................................... 235 Capture (CCP Module) .................................................... 122 CAN Message Time-Stamp ..................................... 123 CCP Pin Configuration ............................................. 122 CCPR1H:CCPR1L Registers ................................... 122 Software Interrupt .................................................... 123 Timer1/Timer3 Mode Selection ................................ 122 Capture (ECCP Module) .................................................. 131 CAN Message Time-Stamp ..................................... 131 Capture/Compare/PWM (CCP) ........................................ 121 Capture Mode. See Capture (CCP Module) CCP1 Module .......................................................... 122 CCPR1H Register .................................................... 122 CCPR1L Register .................................................... 122 Compare Mode. See Compare (CCP Module) Interaction of CCP1 and ECCP1 Modules ............... 122 PWM Mode. See PWM (CCP Module) Timer Resources ..................................................... 122 Ceramic Resonators Ranges Tested .......................................................... 17 Clocking Scheme ............................................................... 41 CLRF ............................................................................... 293 CLRWDT .......................................................................... 293 Code Examples 16 x 16 Signed Multiply Routine ................................ 76 16 x 16 Unsigned Multiply Routine ............................ 76 8 x 8 Signed Multiply Routine .................................... 75 8 x 8 Unsigned Multiply Routine ................................ 75 Changing Between Capture Prescalers ................... 123 Data EEPROM Read ................................................. 61 Data EEPROM Refresh Routine ................................ 62 Data EEPROM Write ................................................. 61 Erasing a FLASH Program Memory Row .................. 70 Fast Register Stack ................................................... 40 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 55 Initializing PORTA ...................................................... 93 Initializing PORTB ...................................................... 95 Initializing PORTC ..................................................... 98 Initializing PORTD ................................................... 100 Initializing PORTE .................................................... 102 Loading the SSPBUF Register ................................ 144 Reading a FLASH Program Memory Word ............... 69 Saving STATUS, WREG and BSR Registers in RAM ...................................... 92 C CALL ................................................................................ 292 CAN Module ..................................................................... 197 Aborting Transmission ............................................. 224 Acknowledge Error ................................................... 233 Baud Rate Registers ................................................ 215 Baud Rate Setting .................................................... 229 Bit Error .................................................................... 233 Bit Time Partitioning ................................................. 229 Bit Timing Configuration Registers ........................... 232 Calculating TQ, Nominal bit Rate and Nominal bit Time .............................................. 230 Configuration Mode .................................................. 222 Control and Status Registers ................................... 199 Controller Register Map ........................................... 221 CRC Error ................................................................ 233 Disable Mode ........................................................... 222 Error Detection ......................................................... 233 Error Modes and Error Counters .............................. 233 Error Modes State Diagram ..................................... 234 Error States .............................................................. 233 Filter Mask Truth (table) ........................................... 228 Form Error ................................................................ 233 Hard Synchronization ............................................... 231 I/O Control Register ................................................. 217 Information Processing Time ................................... 230 Initiating Transmission ............................................. 224 Interrupt Acknowledge ............................................. 235 Interrupt Registers .................................................... 218 Interrupts .................................................................. 234 Bus Activity Wake-up ....................................... 235 Bus-Off ............................................................. 235 Code bits .......................................................... 234 Error ................................................................. 235 Message Error ................................................. 235 Receive ............................................................ 234 Receiver Bus Passive ...................................... 235 Receiver Overflow ............................................ 235 Receiver Warning ............................................ 235 Transmit ........................................................... 234 Transmitter Bus Passive .................................. 235 Transmitter Warning ........................................ 235 Lengthening a bit Period .......................................... 231 Listen Only Mode ..................................................... 222 Loopback Mode ........................................................ 223 Message Acceptance Filters and Masks ....................................................... 212, 228 Message Acceptance Mask and Filter Operation ................................................ 228 Message Reception ................................................. 226 Message Reception Flow Chart ............................... 227 Message Time-Stamping ......................................... 226 Message Transmission ............................................ 223 Modes of Operation .................................................. 222 Normal Mode ............................................................ 222 Oscillator Tolerance ................................................. 232 Overview .................................................................. 197 Phase Buffer Segments ........................................... 230 DS41159B-page 370 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 WIN and ICODE bits Usage in Interrupt Service Routine to Access TX/RX Buffers ....... 201 Writing to FLASH Program Memory .................... 72-73 Code Protection ............................................................... 261 COMF ............................................................................... 294 Comparator Module ......................................................... 245 Analog Input Connection Considerations ................. 249 Associated Registers ............................................... 250 Configuration ............................................................ 246 Effects of a RESET .................................................. 249 External Reference Signal ....................................... 247 Internal Reference Signal ........................................ 247 Interrupts .................................................................. 248 Operation ................................................................. 247 Operation During SLEEP ......................................... 249 Outputs .................................................................... 247 Reference ................................................................ 247 Response Time ........................................................ 247 Comparator Specifications ............................................... 334 Comparator Voltage Reference Module ........................... 251 Accuracy/Error ......................................................... 252 Associated Registers ............................................... 253 Configuring ............................................................... 251 Connection Considerations ...................................... 252 Effects of a RESET .................................................. 252 Operation During SLEEP ......................................... 252 Output Buffer Example ............................................. 253 Compare (CCP Module) ................................................... 124 Associated Registers ............................................... 125 CCP1 Pin Configuration ........................................... 124 CCPR1H:CCPR1L Registers ................................... 124 Software Interrupt .................................................... 124 Special Event Trigger ........................113, 119, 124, 243 Timer1/Timer3 Mode Selection ................................ 124 Compare (ECCP Module) ................................................ 131 Associated Registers ............................................... 131 Special Event Trigger ............................................... 131 Compatible 10-bit Analog-to-Digital Converter (A/D) Module. See A/D. Configuration Mode (CAN Module) .................................. 222 CPFSEQ .......................................................................... 294 CPFSGT ........................................................................... 295 CPFSLT ........................................................................... 295 Crystal Oscillator Capacitor Selection .................................................... 18 DC Characteristics ............................ 327, 328, 329, 330, 331 EEPROM and Enhanced FLASH ............................ 333 DCFSNZ .......................................................................... 297 DECF ............................................................................... 296 DECFSZ .......................................................................... 297 Development Support ...................................................... 319 Development Tool Version Requirements ....................... 367 Device Differences ........................................................... 365 Device Migrations ............................................................ 366 Device Overview .................................................................. 7 Features ...................................................................... 7 Direct Addressing .............................................................. 56 Disable Mode (CAN Module) ........................................... 222 E Electrical Characteristics ................................................. 325 Enhanced Capture/Compare/PWM (ECCP) .................... 129 Auto-Shutdown ........................................................ 140 Capture Mode. See Capture (ECCP Module) Compare Mode. See Compare (ECCP Module) ECCPR1H Register ................................................. 130 ECCPR1L Register .................................................. 130 Interaction of CCP1 and ECCP1 Modules ............... 130 Pin Assignments for Various Modes ........................ 130 PWM Mode. See PWM (ECCP Module) Timer Resources ..................................................... 130 Enhanced CCP Auto-Shutdown ...................................... 140 Enhanced PWM Mode. See PWM (ECCP Module) ........................................................ 132 Errata ................................................................................... 5 Error Recognition Mode (CAN Module) ........................... 222 External Clock Input ........................................................... 19 F Firmware Instructions ...................................................... 277 FLASH Program Memory .................................................. 65 Associated Registers ................................................. 74 Control Registers ....................................................... 66 Erase Sequence ........................................................ 70 Erasing ...................................................................... 70 Operation During Code Protect ................................. 73 Reading ..................................................................... 69 TABLAT (Table Latch) Register ................................. 68 Table Pointer Boundaries Based on Operation ....................... 68 Table Pointer Boundaries .......................................... 68 Table Reads and Table Writes .................................. 65 TBLPTR (Table Pointer) Register .............................. 68 Write Sequence ......................................................... 71 Writing to ................................................................... 71 Protection Against Spurious Writes ................... 73 Unexpected Termination ................................... 73 Write Verify ........................................................ 73 D Data EEPROM Memory ..................................................... 59 Associated Registers ................................................. 63 EEADR Register ........................................................ 59 EECON1 Register ...................................................... 59 EECON2 Register ...................................................... 59 Operation During Code Protect .................................. 62 Protection Against Spurious Writes ........................... 62 Reading ...................................................................... 61 Usage ......................................................................... 62 Write Verify ................................................................ 62 Writing to .................................................................... 61 Data Memory ...................................................................... 44 General Purpose Registers ........................................ 44 Special Function Registers ........................................ 44 Data Memory Map PIC18F248/448 .......................................................... 45 PIC18F258/458 .......................................................... 46 DAW ................................................................................. 296 DC and AC Characteristics Graphs and Tables ............... 355 G GOTO .............................................................................. 298 H Hardware Multiplier ............................................................ 75 Operation ................................................................... 75 Performance Comparison (table) ............................... 75 HS4 (PLL) .......................................................................... 19 2002 Microchip Technology Inc. Preliminary DS41159B-page 371 PIC18FXX8 I I/O Ports ............................................................................. 93 I2C Mode .......................................................................... 150 ACK Pulse ........................................................ 154, 155 Acknowledge Sequence Timing ............................... 174 Baud Rate Generator ............................................... 167 Bus Collision and Arbitration .................................... 175 Bus Collision During a Repeated START Condition ............................................. 179 Bus Collision During a START Condition ................. 177 Bus Collision During a STOP Condition ................... 180 Clock Arbitration ....................................................... 168 Clock Stretching ....................................................... 160 Effect of a RESET .................................................... 175 General Call Address Support ................................. 164 Master Mode ............................................................ 165 Operation ......................................................... 166 Reception ......................................................... 171 Repeated START Condition Timing ................. 170 Master Mode START Condition Timing ................... 169 Master Mode Transmission ...................................... 171 Multi-Master Mode ................................................... 175 Read/Write bit Information (R/W bit) ................ 154, 155 Registers .................................................................. 150 Serial Clock (RC3/SCK/SCL) ................................... 155 Slave Mode .............................................................. 154 Addressing ....................................................... 154 Reception ......................................................... 155 Transmission .................................................... 155 SLEEP Operation ..................................................... 175 STOP Condition Timing ........................................... 174 ICEPIC In-Circuit Emulator .............................................. 320 ID Locations ............................................................. 261, 275 INCF ................................................................................. 298 INCFSZ ............................................................................ 299 In-Circuit Debugger .......................................................... 275 In-Circuit Serial Programming (ICSP) ...................... 261, 275 Indirect Addressing ............................................................ 56 FSR Register .............................................................. 55 INDF Register ............................................................ 55 Operation ................................................................... 55 INFSNZ ............................................................................ 299 Initialization Conditions for All Registers ............................ 30 Instruction Cycle ................................................................. 41 Instruction Flow/Pipelining ................................................. 41 Instruction Format ............................................................ 279 Instruction Set .................................................................. 277 ADDLW .................................................................... 283 ADDWF .................................................................... 283 ADDWFC ................................................................. 284 ANDLW .................................................................... 284 ANDWF .................................................................... 285 BC ............................................................................ 285 BCF .......................................................................... 286 BN ............................................................................ 286 BNC .......................................................................... 287 BNN .......................................................................... 287 BNOV ....................................................................... 288 BNZ .......................................................................... 288 BOV .......................................................................... 291 BRA .......................................................................... 289 BSF .......................................................................... 289 BTFSC ..................................................................... 290 BTFSS ...................................................................... 290 BTG .......................................................................... 291 BZ ............................................................................ 292 CALL ........................................................................ 292 CLRF ....................................................................... 293 CLRWDT ................................................................. 293 COMF ...................................................................... 294 CPFSEQ .................................................................. 294 CPFSGT .................................................................. 295 CPFSLT ................................................................... 295 DAW ........................................................................ 296 DCFSNZ .................................................................. 297 DECF ....................................................................... 296 DECFSZ .................................................................. 297 GOTO ...................................................................... 298 INCF ........................................................................ 298 INCFSZ .................................................................... 299 INFSNZ .................................................................... 299 IORLW ..................................................................... 300 IORWF ..................................................................... 300 LFSR ........................................................................ 301 MOVF ...................................................................... 301 MOVFF .................................................................... 302 MOVLB .................................................................... 302 MOVLW ................................................................... 303 MOVWF ................................................................... 303 MULLW .................................................................... 304 MULWF .................................................................... 304 NEGF ....................................................................... 305 NOP ......................................................................... 305 POP ......................................................................... 306 PUSH ....................................................................... 306 RCALL ..................................................................... 307 RESET ..................................................................... 307 RETFIE .................................................................... 308 RETLW .................................................................... 308 RETURN .................................................................. 309 RLCF ....................................................................... 309 RLNCF ..................................................................... 310 RRCF ....................................................................... 310 RRNCF .................................................................... 311 SETF ........................................................................ 311 SLEEP ..................................................................... 312 SUBFWB ................................................................. 312 SUBLW .................................................................... 313 SUBWF .................................................................... 313 SUBWFB ................................................................. 314 SWAPF .................................................................... 314 TBLRD ..................................................................... 315 TBLWT ..................................................................... 316 TSTFSZ ................................................................... 317 XORLW .................................................................... 317 XORWF ................................................................... 318 Summary Table ....................................................... 280 INTCON Register RBIF bit ...................................................................... 95 Inter-Integrated Circuit. See I2C Interrupt Sources A/D Conversion Complete ....................................... 240 CAN Module ............................................................ 234 Capture Complete (CCP) ......................................... 123 Compare Complete (CCP) ....................................... 124 Interrupt-on-Change (RB7:RB4) ................................ 95 TMR0 Overflow ........................................................ 109 TMR1 Overflow .................................................111, 113 TMR2 to PR2 Match ................................................ 116 TMR2 to PR2 Match (PWM) .............................115, 126 TMR3 Overflow .................................................117, 119 DS41159B-page 372 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 Interrupt-on-Change (RB7:RB4) Flag (RBIF bit) .................................................................... 95 Interrupts ............................................................................ 77 Context Saving During ............................................... 92 Enable Registers ........................................................ 85 Flag Registers ............................................................ 82 INT ............................................................................. 92 PORTB Interrupt-on-Change ..................................... 92 Priority Registers ........................................................ 88 TMR0 ......................................................................... 92 Interrupts, Flag bits CCP1 Flag (CCP1IF bit) ...........................122, 123, 124 Interrupts, Flag bits A/D Converter Flag (ADIF bit) .................................. 239 IORLW ............................................................................. 300 IORWF ............................................................................. 300 SPI Master/Slave Connection .................................. 145 SPI Mode ................................................................. 141 SPI Slave Mode ....................................................... 147 TMR2 Output for Clock Shift .............................115, 116 Typical Connection .................................................. 145 MSSP. See also I2C Mode, SPI Mode. MULLW ............................................................................ 304 MULWF ............................................................................ 304 N NEGF ............................................................................... 305 NOP ................................................................................. 305 Normal Operation Mode (CAN Module) ........................... 222 O OPCODE Field Descriptions ............................................ 278 OPTION_REG Register PSA bit ..................................................................... 109 T0CS bit ................................................................... 109 T0PS2:T0PS0 bits ................................................... 109 T0SE bit ................................................................... 109 Oscillator Effects of SLEEP Mode ............................................. 23 Power-up Delays ....................................................... 23 Switching Feature ...................................................... 20 System Clock Switch bit ............................................ 20 Transitions ................................................................. 21 Oscillator Configurations .................................................... 17 Crystal Oscillator, Ceramic Resonators ..................... 17 EC .............................................................................. 17 ECIO .......................................................................... 17 HS .............................................................................. 17 HS4 ............................................................................ 17 LP .............................................................................. 17 RC ........................................................................17, 18 RCIO .......................................................................... 17 XT .............................................................................. 17 Oscillator Selection .......................................................... 261 Oscillator, Timer1 .............................................. 111, 113, 119 Oscillator, WDT ................................................................ 268 K KEELOQ Evaluation and Programming Tools ................... 322 L LFSR ................................................................................ 301 Listen Only Mode (CAN Module) ..................................... 222 Lookup Tables .................................................................... 43 Computed GOTO ....................................................... 43 Table Reads/Table Writes ......................................... 43 Loopback Mode (CAN Module) ........................................ 222 Low Voltage Detect .......................................................... 255 Characteristics ......................................................... 332 Characteristics (diagram) ......................................... 332 Current Consumption ............................................... 259 Effects of a RESET .................................................. 259 Operation ................................................................. 258 Operation During SLEEP ......................................... 259 Reference Voltage Set Point .................................... 259 Typical Application ................................................... 255 Low Voltage ICSP Programming ..................................... 275 LVD. See Low Voltage Detect. M Master Synchronous Serial Port (MSSP). See MSSP. Master Synchronous Serial Port. See MSSP. Memory Organization ......................................................... 37 Data Memory ............................................................. 44 Internal Program Memory Operation ......................... 37 Program Memory ....................................................... 37 Migrating from other PICmicro Devices ........................... 366 MOVF ............................................................................... 301 MOVFF ............................................................................. 302 MOVLB ............................................................................. 302 MOVLW ............................................................................ 303 MOVWF ........................................................................... 303 MPLAB C17 and MPLAB C18 C Compilers ..................... 319 MPLAB ICD In-Circuit Debugger ...................................... 321 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ........................ 320 MPLAB Integrated Development Environment Software .............................................. 319 MPLINK Object Linker/MPLIB Object Librarian ............... 320 MSSP ............................................................................... 141 Control Registers ..................................................... 141 Enabling SPI I/O ...................................................... 145 I2C Mode Operation ................................................. 154 Operation ................................................................. 144 Overview .................................................................. 141 SPI Master Mode ..................................................... 146 P Packaging Information ..................................................... 357 Details ...................................................................... 359 Marking .................................................................... 357 Parallel Slave Port (PSP) ..........................................100, 105 Associated Registers ............................................... 106 PORTD .................................................................... 105 PSP Mode Select (PSPMODE) bit .......................... 100 RE2/CS .................................................................... 105 PIC18FXX8 Voltage-Frequency Graph (Industrial) ................................................................ 326 PIC18LFXX8 Voltage-Frequency Graph (Industrial) ................................................................ 326 PICDEM 1 Low Cost PICmicro Demonstration Board ............................................... 321 PICDEM 17 Demonstration Board ................................... 322 PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 321 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ............................................... 322 PICSTART Plus Entry Level Development Programmer ............................................................. 321 2002 Microchip Technology Inc. Preliminary DS41159B-page 373 PIC18FXX8 Pin Functions MCLR/VPP .................................................................. 10 OSC1/CLKI ................................................................ 10 OSC2/CLKO/RA6 ....................................................... 10 RA0/AN0/CVREF ........................................................ 11 RA1/AN1 .................................................................... 11 RA2/AN2/VREF- .......................................................... 11 RA3/AN3/VREF+ ......................................................... 11 RA4/T0CKI ................................................................. 11 RA5/AN4/SS/LVDIN ................................................... 11 RA6 ............................................................................ 11 RB0/INT0 ................................................................... 12 RB1/INT1 ................................................................... 12 RB2/CANTX ............................................................... 12 RB3/CANRX ............................................................... 12 RB4 ............................................................................ 12 RB5/PGM ................................................................... 12 RB6/PGC ................................................................... 12 RB7/PGD ................................................................... 12 RC0/T1OSO/T1CKI .................................................... 13 RC1/T1OSI ................................................................. 13 RC2/CCP1 ................................................................. 13 RC3/SCK/SCL ............................................................ 13 RC4/SDI/SDA ............................................................. 13 RC5/SDO ................................................................... 13 RC6/TX/CK ................................................................ 13 RC7/RX/DT ................................................................ 13 RD0/PSP0/C1IN+ ...................................................... 14 RD1/PSP1/C1IN- ....................................................... 14 RD2/PSP2/C2IN+ ...................................................... 14 RD3/PSP3/C2IN- ....................................................... 14 RD4/PSP4/ECCP/PA ................................................. 14 RD5/PSP5/PB ............................................................ 14 RD6/PSP6/PC ............................................................ 14 RD7/PSP7/PD ............................................................ 14 RE0/AN5/RD .............................................................. 15 RE1/AN6/WR/C1OUT ................................................ 15 RE2/AN7/CS/C2OUT ................................................. 15 Pinout I/O Descriptions ...................................................... 10 Pointer, FSRn ..................................................................... 55 POP .................................................................................. 306 POR. See Power-on Reset. PORTA Associated Register Summary ................................... 94 Functions .................................................................... 94 LATA Register ............................................................ 93 PORTA Register ........................................................ 93 TRISA Register .......................................................... 93 PORTB Associated Registers ................................................. 97 Functions .................................................................... 97 LATB Register ............................................................ 95 PORTB Register ........................................................ 95 RB7:RB4 Interrupt-on-Change Flag (RBIF bit) ............................................................ 95 TRISB Register .......................................................... 95 PORTC Associated Registers ................................................. 99 Functions .................................................................... 99 LATC Register ............................................................ 98 PORTC Register ........................................................ 98 RC3/SCK/SCL Pin ................................................... 155 RC7/RX/DT Pin ........................................................ 183 TRISC Register .................................................. 98, 181 PORTD Associated Register Summary ................................ 101 Functions ................................................................. 101 LATD Register ......................................................... 100 Parallel Slave Port (PSP) Function .......................... 100 PORTD Register ...................................................... 100 TRISD Register ........................................................ 100 PORTE Associated Register Summary ................................ 104 Functions ................................................................. 103 LATE Register ......................................................... 102 PORTE Register ...................................................... 102 PSP Mode Select (PSPMODE) bit .......................... 100 RE2/CS .................................................................... 105 TRISE Register ........................................................ 102 Postscaler, WDT Assignment (PSA bit) ............................................... 109 Rate Select (T0PS2:T0PS0 bits) ............................. 109 Power-down Mode. See SLEEP Power-on Reset (POR) ...............................................26, 261 MCLR ......................................................................... 26 Oscillator Start-up Timer (OST) ..........................26, 261 PLL Lock Time-out ..................................................... 26 Power-up Timer (PWRT) ....................................26, 261 Time-out Sequence ................................................... 27 Power-up Delays OSC1 and OSC2 Pin States in SLEEP Mode ........... 23 Prescaler, Capture ........................................................... 123 Prescaler, Timer0 ............................................................. 109 Assignment (PSA bit) ............................................... 109 Rate Select (T0PS2:T0PS0 bits) ............................. 109 Prescaler, Timer2 ............................................................. 126 PRO MATE II Universal Device Programmer .................. 321 Product Identification System .......................................... 381 Program Counter PCL Register ............................................................. 40 PCLATH Register ...................................................... 40 PCLATU Register ...................................................... 40 Program Memory ............................................................... 37 Fast Register Stack ................................................... 40 Instructions ................................................................ 41 Two-Word .......................................................... 43 Map and Stack for PIC18F248/448 ........................... 37 Map and Stack for PIC18F258/458 ........................... 37 PUSH and POP Instructions ...................................... 40 Return Address Stack ................................................ 38 Return Stack Pointer (STKPTR) ................................ 38 Stack Full/Underflow Resets ...................................... 40 Top-of-Stack Access .................................................. 38 Program Verification and Code Protection ....................... 272 Associated Registers Summary ............................... 272 Configuration Register Protection ............................ 275 Data EEPROM Code Protection .............................. 275 Program Memory Code Protection .......................... 273 Programming, Device Instructions ................................... 277 PUSH ............................................................................... 306 PWM (CCP Module) ........................................................ 126 CCPR1H:CCPR1L Registers ................................... 126 Duty Cycle ............................................................... 126 Example Frequencies/Resolutions .......................... 127 Output Diagram ....................................................... 126 Period ...................................................................... 126 Registers Associated with PWM and Timer2 ........... 127 Setup for PWM Operation ........................................ 127 TMR2 to PR2 Match .........................................115, 126 DS41159B-page 374 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 PWM (ECCP Module) ...................................................... 132 Associated Registers ............................................... 139 Direction Change in Full-Bridge Output Mode ......... 136 Enhanced CCP Auto-Shutdown ............................... 140 Full-Bridge Application Example .............................. 136 Full-Bridge Mode ...................................................... 135 Full-Bridge PWM Output Diagram ........................... 135 Half-Bridge Mode ..................................................... 134 Half-Bridge Output Diagram ..................................... 134 Half-Bridge Output Mode Applications Example ...... 134 Output Configurations .............................................. 132 Output Polarity Configuration ................................... 138 Output Relationships Diagram ................................. 133 Programmable Deadband Delay .............................. 138 PWM Direction Change at Near 100% Duty Cycle Diagram ......................................... 137 PWM Direction Change Diagram ............................. 137 Setup for PWM Operation ........................................ 139 Standard Mode ........................................................ 132 Start-up Considerations ........................................... 138 System Implementation ........................................... 138 EECON1 (EEPROM Control 1) ............................60, 67 INTCON (Interrupt Control) ........................................ 79 INTCON2 (Interrupt Control 2) ................................... 80 INTCON3 (Interrupt Control 3) ................................... 81 IPR1 (Peripheral Interrupt Priority 1) ......................... 88 IPR2 (Peripheral Interrupt Priority 2) ......................... 89 IPR3 (Peripheral Interrupt Priority 3) ......................... 90 IPR3 (Peripheral Interrupt Priority) .......................... 220 LVDCON (LVD Control) ........................................... 257 OSCCON (Oscillator Control) .................................... 20 PIE1 (Peripheral Interrupt Enable 1) .......................... 85 PIE2 (Peripheral Interrupt Enable 2) .......................... 86 PIE3 (Peripheral Interrupt Enable 3) .......................... 87 PIE3 (Peripheral Interrupt Enable) ........................... 219 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 82 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 83 PIR3 (Peripheral Interrupt Flag) ............................... 218 PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 84 RCON (Reset Control) ..........................................58, 91 RCSTA (USART Receive Status) ............................ 182 RXB0CON (Receive Buffer 0 Control) ..................... 208 RXB1CON (Receive Buffer 1 Control) ..................... 209 RXBnDLC (Receive Buffer n Data Length Code) .......................................... 211 RXBnDm (Receive Buffer n Data Field Byte m) ................................................... 211 RXBnEIDH (Receive Buffer n Extended Identifier, High Byte) ........................................................ 210 RXBnEIDL (Receive Buffer n Extended Identifier, Low Byte) ......................................... 210 RXBnSIDH (Receive Buffer n Standard Identifier, High Byte) ........................................ 209 RXBnSIDL (Receive Buffer n Standard Identifier, Low Byte) ......................................... 210 RXERRCNT (Receive Error Count) ......................... 212 RXFnEIDH (Receive Acceptance Filter n Extended Identifier, High Byte) ........................ 213 RXFnEIDL (Receive Acceptance Filter n Extended Identifier, Low Byte) ......................... 213 RXFnSIDH (Receive Acceptance Filter n Standard Identifier Filter, High Byte) ............... 212 RXFnSIDL (Receive Acceptance Filter n Standard Identifier Filter, Low Byte) ................ 212 RXMnEIDH (Receive Acceptance Mask n Extended Identifier Mask, High Byte) .............. 214 RXMnEIDL (Receive Acceptance Mask n Extended Identifier Mask, Low Byte) ............... 214 RXMnSIDH (Receive Acceptance Mask n Standard Identifier Mask, High Byte) ............... 213 RXMnSIDL (Receive Acceptance Mask n Standard Identifier Mask, Low Byte) ................ 214 SSPCON1 (MSSP Control 1) .................................. 143 SSPCON1 (MSSP Control 1) (I2C Mode ................. 152 SSPCON2 (MSSP Control 2) (I2C Mode) ................ 153 SSPSTAT (MSSP Status) ........................................ 142 SSPSTAT (MSSP Status) (I2C Mode) ..................... 151 STATUS .................................................................... 57 STKPTR (Stack Pointer) ............................................ 39 T0CON (Timer0 Control) ......................................... 107 T1CON (Timer1 Control) ......................................... 111 T2CON (Timer2 Control) ......................................... 115 T3CON (Timer3 Control) ......................................... 117 TRISE (PORTE Direction/PSP Control) .................. 103 TXBnCON (Transmit Buffer n Control) .................... 204 Q Q Clock ............................................................................ 126 R RAM. See Data Memory. RCALL .............................................................................. 307 RCON Register Significance of Status bits vs. Initialization Condition ........................................ 27 RCSTA Register ............................................................... 181 SPEN bit .................................................................. 181 Receiver Warning ............................................................. 235 Register File ....................................................................... 44 Register File Summary ....................................................... 49 Registers ADCON0 (A/D Control 0) ......................................... 237 ADCON1 (A/D Control 1) ......................................... 238 BRGCON1 (Baud Rate Control 1) ........................... 215 BRGCON2 (Baud Rate Control 2) ........................... 216 BRGCON3 (Baud Rate Control 3) ........................... 217 CANCON (CAN Control) .......................................... 199 CANSTAT (CAN Status) .......................................... 200 CCP1CON (CCP1 Control) ...................................... 121 CIOCON (CAN I/O Control) ..................................... 217 CMCON (Comparator Control) ................................ 245 COMSTAT (CAN Communication Status) ............... 203 CONFIG1H (Configuration 1 High) .......................... 262 CONFIG2H (Configuration 2 High) .......................... 263 CONFIG2L (Configuration 2 Low) ............................ 262 CONFIG4L (Configuration 4 Low) ............................ 263 CONFIG5H (Configuration 5 High) .......................... 264 CONFIG5L (Configuration 5 Low) ............................ 264 CONFIG6H (Configuration 6 High) .......................... 265 CONFIG6L (Configuration 6 Low) ............................ 265 CONFIG7H (Configuration 7 High) .......................... 266 CONFIG7L (Configuration 7 Low) ............................ 266 CVRCON (Comparator Voltage Reference Control) ........................................... 251 Device ID Register 1 ................................................ 267 Device ID Register 2 ................................................ 267 ECCP1CON (ECCP1 Control) ................................. 129 ECCP1DEL (PWM Delay) ........................................ 138 ECCPAS (Enhanced Capture/Compare/PWM Auto-Shutdown Control) ................................... 140 2002 Microchip Technology Inc. Preliminary DS41159B-page 375 PIC18FXX8 TXBnDLC (Transmit Buffer n Data Length Code) ................................................... 207 TXBnDm (Transmit Buffer n Data Field Byte m) ........................................... 206 TXBnEIDH (Transmit Buffer n Extended Identifier, High Byte) ........................ 205 TXBnEIDL (Transmit Buffer n Extended Identifier, Low Byte) ......................... 206 TXBnSIDH (Transmit Buffer n Standard Identifier, High Byte) ......................... 205 TXBnSIDL (Transmit Buffer n Standard Identifier, Low Byte) .......................... 205 TXERRCNT (Transmit Error Count) ......................... 207 TXSTA (USART Transmit Status) ............................ 181 WDTCON (Watchdog Timer Control) ....................... 268 RESET ............................................................... 25, 261, 307 MCLR Reset During Normal Operation ...................... 25 MCLR Reset During SLEEP ...................................... 25 Power-on Reset (POR) .............................................. 25 Programmable Brown-out Reset (PBOR) .................. 25 RESET Instruction ...................................................... 25 Stack Full Reset ......................................................... 25 Stack Underflow Reset ............................................... 25 Watchdog Timer (WDT) Reset ................................... 25 RETFIE ............................................................................ 308 RETLW ............................................................................. 308 RETURN .......................................................................... 309 Revision History ............................................................... 365 RLCF ................................................................................ 309 RLNCF ............................................................................. 310 RRCF ............................................................................... 310 RRNCF ............................................................................. 311 Slave Select Synchronization .................................. 147 SLEEP Operation .................................................... 149 SPI Clock ................................................................. 146 SSPBUF Register .................................................... 146 SSPSR Register ...................................................... 146 SSPOV bit ........................................................................ 171 SSPSTAT Register R/W bit ..............................................................154, 155 SUBFWB ......................................................................... 312 SUBLW ............................................................................ 313 SUBWF ............................................................................ 313 SUBWFB ......................................................................... 314 SWAPF ............................................................................ 314 T Table Pointer Operations (table) ........................................ 68 TBLRD ............................................................................. 315 TBLWT ............................................................................. 316 Timer0 .............................................................................. 107 16-bit Mode Timer Reads and Writes ...................... 109 Clock Source Edge Select (T0SE bit) ...................... 109 Clock Source Select (T0CS bit) ............................... 109 Operation ................................................................. 109 Overflow Interrupt .................................................... 109 Prescaler .................................................................. 109 Prescaler. See Prescaler, Timer0 Switching Prescaler Assignment ............................. 109 Timer1 .............................................................................. 111 Associated Registers ............................................... 113 Operation ................................................................. 112 Oscillator ...........................................................111, 113 Overflow Interrupt .............................................111, 113 Special Event Trigger (CCP) ............................113, 124 Special Event Trigger (ECCP) ................................. 131 TMR1H Register ...................................................... 111 TMR1L Register ....................................................... 111 TMR3L Register ....................................................... 117 Timer2 .............................................................................. 115 Associated Registers ............................................... 116 Operation ................................................................. 115 Postscaler. See Postscaler, Timer2 PR2 Register ....................................................115, 126 Prescaler. See Prescaler, Timer2 SSP Clock Shift ................................................115, 116 TMR2 Register ......................................................... 115 TMR2 to PR2 Match Interrupt ...................115, 116, 126 Timer3 .............................................................................. 117 Associated Registers ............................................... 119 Operation ................................................................. 118 Oscillator .................................................................. 119 Overflow Interrupt .............................................117, 119 Special Event Trigger (CCP) ................................... 119 TMR3H Register ...................................................... 117 Timing Conditions ............................................................ 336 Load Conditions for Device Specifications .............. 336 Temperature and Voltage Specifications - AC .......................................... 336 Timing Diagrams A/D Conversion ........................................................ 353 Acknowledge Sequence .......................................... 174 Baud Rate Generator with Clock Arbitration ............ 168 BRG Reset Due to SDA Arbitration During START Condition ............................................. 178 Brown-out Reset (BOR) and Low Voltage Detect ................................................. 339 S Sales and Support ............................................................ 381 SCI. See USART SCK pin ............................................................................ 141 SDI pin ............................................................................. 141 SDO pin ............................................................................ 141 Serial Clock (SCK) pin ..................................................... 141 Serial Communication Interface. See USART Serial Peripheral Interface. See SPI SETF ................................................................................ 311 Slave Select (SS) Pin ....................................................... 141 Slave Select Synchronization ........................................... 147 Slave Select, SS pin ......................................................... 141 SLEEP .............................................................. 261, 270, 312 Software Simulator (MPLAB SIM) .................................... 320 Special Event Trigger. See Compare Special Features of the CPU ............................................ 261 Configuration bits ..................................................... 261 Configuration bits and Device IDs ............................ 261 Configuration Registers .................................... 262-267 Special Function Register Map .......................................... 47 Special Function Registers ................................................ 44 SPI Mode Associated Registers ............................................... 149 Bus Mode Compatibility ........................................... 149 Effects of a RESET .................................................. 149 Master Mode ............................................................ 146 Master/Slave Connection ......................................... 145 Serial Clock .............................................................. 141 Serial Data In (SDI) pin ............................................ 141 Serial Data Out (SDO) pin ........................................ 141 Slave Mode .............................................................. 147 Slave Select ............................................................. 141 DS41159B-page 376 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 Bus Collision During a Repeated START Condition (Case 1) .............................. 179 Bus Collision During a Repeated START Condition (Case2) ............................... 179 Bus Collision During a STOP Condition (Case 1) ........................................... 180 Bus Collision During a STOP Condition (Case 2) ........................................... 180 Bus Collision During START Condition (SCL = 0) ......................................... 178 Bus Collision During START Condition (SDA Only) ....................................... 177 Bus Collision for Transmit and Acknowledge .................................................... 176 Capture/Compare/PWM (CCP1 and ECCP1) ......................................... 341 CLKO and I/O .......................................................... 338 Clock Synchronization ............................................. 161 External Clock .......................................................... 337 First START bit Timing ............................................. 169 I2C Bus Data ............................................................ 347 I2C Bus START/STOP bits ...................................... 347 I2C Master Mode (Reception, 7-bit Address) ........... 173 I2C Master Mode (Transmission, 7 or 10-bit Address) ................................................. 172 I2C Slave Mode (Transmission, 10-bit Address) ................................................. 159 I2C Slave Mode (Transmission, 7-bit Address) ................................................... 157 I2C Slave Mode SEN = 1 (Reception, 10-bit Address) ................................................. 163 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address) ................................................. 158 I2C Slave Mode with SEN = 0 (Reception, 7-bit Address) ................................................... 156 I2C Slave Mode with SEN = 1 (Reception, 7-bit Address) ................................................... 162 Low Voltage Detect .................................................. 258 Master SSP I2C Bus Data ........................................ 349 Master SSP I2C Bus START/STOP bits .................. 349 Parallel Slave Port (PIC18F248 and PIC18F458) ............................................... 342 Parallel Slave Port Read Waveforms ....................... 106 Parallel Slave Port Write Waveforms ....................... 105 Repeat START Condition ........................................ 170 RESET, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ............................................................ 339 Slave Mode General Call Address Sequence (7 or 10-bit Address Mode) .............................. 164 Slave Synchronization ............................................. 147 Slow Rise Time (MCLR Tied to VDD Via RC Network) ................................................ 29 SPI Master Mode (CKE = 0) .................................... 343 SPI Master Mode (CKE = 1) .................................... 344 SPI Mode (Master Mode) ......................................... 146 SPI Mode (Slave Mode with CKE = 0) ..................... 148 SPI Mode (Slave Mode with CKE = 1) ..................... 148 SPI Slave Mode (CKE = 0) ...................................... 345 SPI Slave Mode (CKE = 1) ...................................... 346 STOP Condition Receive or Transmit Mode ............ 175 Time-out Sequence on POR w/ PLL Enabled (MCLR Tied to VDD Via RC Network) ................ 29 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 1 ....................... 28 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 2 ...................... 28 Time-out Sequence on Power-up (MCLR Tied to VDD Via RC Network) ................ 28 Timer0 and Timer1 External Clock .......................... 340 Transition Between Timer1 and OSC1 (HS with PLL) .................................................... 22 Transition Between Timer1 and OSC1 (HS, XT, LP) ...................................................... 21 Transition Between Timer1 and OSC1 (RC, EC) ............................................................ 22 Transition from OSC1 to Timer1 Oscillator ................ 21 USART Asynchronous Reception ............................ 190 USART Asynchronous Transmission ...................... 188 USART Asynchronous Transmission (Back to Back) ................................................. 188 USART Synchronous Receive (Master/Slave) ........ 351 USART Synchronous Reception (Master Mode, SREN) ..................................... 193 USART Synchronous Transmission ........................ 192 USART Synchronous Transmission (Master/Slave) ................................................. 351 USART Synchronous Transmission (Through TXEN) .............................................. 192 Wake-up from SLEEP via Interrupt .......................... 271 Timing Diagrams and Specifications ............................... 337 A/D Conversion Requirements ................................ 353 Capture/Compare/PWM Requirements (CCP1 and ECCP1) ......................................... 341 CLKO and I/O Timing Requirements ....................... 338 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 343 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 344 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 345 Example SPI Slave Mode Requirements (CKE = 1) 346 External Clock Timing Requirements ...................... 337 I2C Bus Data Requirements (Slave Mode) .............. 348 I2C Bus START/STOP bits Requirements (Slave Mode) ................................................... 347 Master SSP I2C Bus Data Requirements ................ 350 Master SSP I2C Bus START/STOP bits Requirements .................................................. 349 Parallel Slave Port Requirements (PIC18F248 and PIC18F458) .......................... 342 PLL Clock ................................................................ 338 RESET, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low Voltage Detect Requirements ........... 339 Timer0 and Timer1 External Clock Requirements ........................................ 340 USART Synchronous Transmission Requirements .................................................. 351 TSTFSZ ........................................................................... 317 TXSTA Register BRGH bit ................................................................. 183 2002 Microchip Technology Inc. Preliminary DS41159B-page 377 PIC18FXX8 U USART ............................................................................. 181 Asynchronous Mode ................................................ 187 Asynchronous Reception ................................. 189, 190 Asynchronous Transmission .................................... 187 Associated Registers ....................................... 188 Baud Rate Generator (BRG) .................................... 183 Associated Registers ....................................... 183 Baud Rate Error, Calculating ........................... 183 Baud Rate Formula .......................................... 183 Baud Rates for Asynchronous Mode (BRGH = 0) .............................................. 185 Baud Rates for Asynchronous Mode (BRGH = 1) .............................................. 186 Baud Rates for Synchronous Mode ................. 184 High Baud Rate Select (BRGH bit) .................. 183 Sampling .......................................................... 183 Serial Port Enable (SPEN) bit .................................. 181 Setting Up 9-bit Mode with Address Detect ............. 189 Synchronous Master Mode ...................................... 191 Synchronous Master Reception ............................... 193 Associated Registers ....................................... 193 Synchronous Master Transmission .......................... 191 Associated Registers ....................................... 191 Synchronous Slave Mode ........................................ 194 Synchronous Slave Reception ......................... 194, 195 Synchronous Slave Transmission Associated Registers ....................................... 195 Synchronous Slave Transmit ................................... 194 V Voltage Reference Specifications .................................... 334 W Wake-up from SLEEP ...............................................261, 270 Using Interrupts ....................................................... 270 Watchdog Timer (WDT) ............................................261, 268 Associated Registers ............................................... 269 Control Register ....................................................... 268 Postscaler ................................................................ 269 Programming Considerations .............................66, 268 RC Oscillator ............................................................ 268 Time-out Period ....................................................... 268 WCOL ...............................................................169, 171, 174 WCOL Status Flag ........................................................... 169 WDT. See Watchdog Timer. ............................................ 268 WWW, On-Line Support ...................................................... 5 X XORLW ............................................................................ 317 XORWF ........................................................................... 318 DS41159B-page 378 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 013001 Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2002 Microchip Technology Inc. Preliminary DS41159B-page 379 PIC18FXX8 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18FXX8 Questions: 1. What are the best features of this document? Y N Literature Number: DS41159B FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS41159B-page 380 Preliminary 2002 Microchip Technology Inc. PIC18FXX8 PIC18FXX8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) PIC18LF258 - I/L 301 = Industrial temp., PLCC package, Extended VDD limits, QTP pattern #301. PIC18LF458 - I/PT = Industrial temp., TQFP package, Extended VDD limits. PIC18F258 - E/L = Extended temp., PLCC package, normal VDD limits. Device PIC18F248/258(1), PIC18F448/458(1), PIC18F248/258T(2), PIC18F448/458T(2); VDD range 4.2V to 5.5V PIC18LF248/258(1), PIC18LF448/458(1), PIC18LF248/258T(2), PIC18LF448/458T(2); VDD range 2.0V to 5.5V c) Temperature Range I E = -40C to +85C = -40C to +125C (Industrial) (Extended) Note 1: 2: Package PT L SO SP P = = = = = TQFP (Thin Quad Flatpack) PLCC SOIC Skinny Plastic DIP PDIP F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel PLCC, and TQFP packages only. Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. Preliminary DS41159B-page 381 M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Beijing Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Shenzhen Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 New York 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 Germany Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 China - Hong Kong SAR Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 05/16/02 DS41159B-page 382 Preliminary 2002 Microchip Technology Inc. |
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